Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

why lec performed at various steps

Status
Not open for further replies.

narureddyk

Newbie level 6
Joined
Feb 17, 2011
Messages
14
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,361
why logical equivalence check is performed at various steps in some designs?
 

As we go through various design step original netlist is modified many times for example for optimization etc. LEC check whether modified netlist still performs intended function or not i.e. it is logically equivalent to original net list.
 
Is lec performed on the flattened netlist or hierarchical netlist if yes why? if no why?
 

LEC can be performed both on hierarchical netlist and flat netlist.. Equivalence check is done to check whether netlist (after synthesis optimisation, post cts, post route) is logically equivalent to golden RTL or netlist..
 
Netlist is changed in both the cases. LEC is performed if there is change in Netlist. So LEC is performed in both the cases.
 
what is the meaning of golden exactly
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top