why latency in behvioral simulation is different in comparence with post&rout simulat

[h.m]

why latency in behvioral simulation is different in comparence with post&rout simulat

hi, i have a 10 ns clock in my simulation, i get my output after 30 clk, as i expect in behavioral simulation but i get it after 40 clk in post&rout simulation, so what is this difference for?

 

[K-J]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

hi, i have a 10 ns clock in my simulation, i get my output after 30 clk, as i expect in behavioral simulation but i get it after 40 clk in post&rout simulation, so what is this difference for?

Because post-route models reality and in reality, nothing ever happens instantly. In your behavioral simulation, things happen instantly.

Kevin Jennings

 

[h.m]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

so i have some wrong output before the right one,it will cause problem in my implementation, because now i have just one input, and it may differ with my input, so when i should get my output from this design? how i should know the max latency, that work with all the inputs?because i think i should know when i should give my next input to the circuit, isn't it?

 

[std_match]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

The real circuit should behave as the behavioral simulation. Do you have access to the complete source code, or do you use IP-blocks with only simulation models?

 

[h.m]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

excuse for asking this question, but what do u mean by source code? do u mean my codes?
no i do not use any cores

 

[std_match]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

excuse for asking this question, but what do u mean by source code? do u mean my codes?
no i do not use any cores

With "source code" I mean the VHDL or Verilog code. I think we must see it to help you.

 

[h.m]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

so you mean that this differences should not happen?in these simulations?
and i should correct my codes?

 

[TrickyDicky]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

so you mean that this differences should not happen?in these simulations?
and i should correct my codes?

The fact you have differences between gate level simulation and function simulation means there is a problem in your code. Without seeing the code, we cannot tell you what the problem is.

 

[h.m]

Re: why latency in behvioral simulation is different in comparence with post&rout sim

sorry for my late, i attach my source code.