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Why latch make ASIC flow difficult?

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davyzhu

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asic flow

Hello all,

Why latch make ASIC flow difficult? And does others do the same?
Thanks!

davy
 

omid219

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why avoid latch in your design

Makes difficulty in test & timing analysis
 

ikru26

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basic asic flow

this is what latch up .....

If one were to draw a line from the source or drain of the PFET through the well, through the substrate, to the source or drain of the NFET, the line would pass through a PNPN stack layers. These four layers form a parasitic silicon controlled rectifier(SCR) structure that, if triggered, can LATCH UP, leading to a catastrophic failure. Layout guidelines for connecting power supplies to well and substrate spoil the gain of this parasitic device to prevent it from becoming a problem.

u can get further information on

Principles of CMOS Vlsi Design By Weste and Kamran ..in this book
 

eda_wiz

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ikru26 said:
this is what latch up .....

If one were to draw a line from the source or drain of the PFET through the well, through the substrate, to the source or drain of the NFET, the line would pass through a PNPN stack layers. These four layers form a parasitic silicon controlled rectifier(SCR) structure that, if triggered, can LATCH UP, leading to a catastrophic failure. Layout guidelines for connecting power supplies to well and substrate spoil the gain of this parasitic device to prevent it from becoming a problem.

u can get further information on

Principles of CMOS Vlsi Design By Weste and Kamran ..in this book

He is asking about Latch. But you are talkinga bout CMOS Latch-up .. totally different things buddy.
 

tony_taoyh

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Currently syntheis, P&R, STA tools are capable
to deal with latch based design;
you can refer to the reference of those tools..

But it is not recommended to use it if you can
avoid it,,
Tony
 

tony_taoyh

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Actually, Latch can be used in High Speed Digital Design....

This is one research interest now...

But in your design for commercial ASIC, it is best
to avoid it..
 

arp

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The main problem by usinf latch is timing analysis as above said.
and also for testing it creates lot of problems
better avoid latch
 

beowulf

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Latches allow glitches and other noise to pass to the o/p. Since the time window is greater than that of FF, its difficult to capture a rapidly changing signal.

But they are used to fix setup time violations, experienced ppl-> please correct me if I am wrong. can anybody please give me more information on this.

Thanks,
Beowulf
 

kxchorus

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except for timing and DFT issues, Latch based design is often easy make circuit fail. This will need carefully designed and balanced for each path delay.

One example is that Latch is easy to cause combinational loop back and easy to cause osc effects. Often latch based circuit is using two clock interleaved. This can really help to improve the clock spped.
 

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