ikru26 said:this is what latch up .....
If one were to draw a line from the source or drain of the PFET through the well, through the substrate, to the source or drain of the NFET, the line would pass through a PNPN stack layers. These four layers form a parasitic silicon controlled rectifier(SCR) structure that, if triggered, can LATCH UP, leading to a catastrophic failure. Layout guidelines for connecting power supplies to well and substrate spoil the gain of this parasitic device to prevent it from becoming a problem.
u can get further information on
Principles of CMOS Vlsi Design By Weste and Kamran ..in this book