Why is this Shift in Folded Cascode Structure

[kumar123]

Hi,
I have designed (Nmos input current mirror o/p stage) Folded cascode signle ended stage, after doing simulations i have observed different issue like

it can operate over Vcm of 0.75 to 1.8V (as supply vltage is 1.8V)
with this Vcm i am varying Vdiff also to make sure till what value all transistors are in saturation.

IP = Vcm + Vdiff
IN = Vcm - Vdiff
Vdiff -----> vary from -50mV to +50mV @ different Vcm

1st Experiment:
Vcm = 0.75 Vdiff vary between -50mV to +50mV
Results: all transistors are in saturation between -1mv to +1mv
2nd Experiment:
Vcm = 1.8 Vdiff vary between -50mV to +50mV
Results: all transistors are in saturation between -0.25mv to +1.75mv

why is the shift from left to right (instead of uniform around Vdiff =0 Axis) as Vcm changed to some high value?

can any one comment on this ?

 

[malizevzek]

hard to say without simulation.

this asymmetry leads to a conclusion that the only part of the circuit that is not symmetrical causes the problem - the output current mirror for single-ended output. One possibility is that when your Vcm is high, biasing current for the input differential pair becomes higher (if the output resistance of the current source transistors small), so the more critical side of the output current mirror (the one that is not the output) cannot provide such a current with voltage headroom allowed. In that case, one should use bigger transistors in output, and better current source at input.

Once more, it's hard to say more without simulation.

 

[luochuan]

give more information about your circuit!

 

[kumar123]

Hi

attached the Schematic, where in though i used Transistors Aspect ratio is identical i am observing slight deviation in current through them as listed below , is that causing the problem of unsymmetrical Vdiff (Vp-Vn) ?
if so how to resolve this ?

below are the operating point currents through respective transistors

@ Vcm = 0.75V Vdiff =0
----------------------------
M9 40.0289 uA (Tranistor for VP)
M10 40.0276 uA (Tranistor for VN)

M0 -101.759 uA
M1 -101.748 uA

@ Vcm = 1.8V Vdiff =0
----------------------------

M9 42.6044 uA
M10 42.5979 uA

M0 -101.836 uA
M1 -101.827 uA

thanks
kiran

 

[malizevzek]

What are the values of Vout1 and Vout2 for Vcm=0.75V and Vcm=1.8V?

 

[kumar123]

What are the values of Vout1 and Vout2 for Vcm=0.75V and Vcm=1.8V?

i have not noted but difference between them at 0.75 and 1.8 Vcm differs less than 1mV

 

[DenisMark]

This effect is related with CMRR. This means that by changing of VCM you changes input related offset of amplifier.
To improve CMRR you should to move in both this directions:
1) Make better tail current source. You need current source with high Rout. So don't use minimum length transistors in tail current source circuit. It's better to use cascode or regulated current source.
2) Decrease input related offset by mean of input differential pair sizes.