A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module.
The Type C time base becomes the MSWord of the combined timer and the Type B time base is
the LSWord.
When configured for 32-bit operation, the control bits for the Type B time base control the operation
of the 32-bit timer. The control bits in the TxCON register for the Type C time base have no effect.
For interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and
interrupt priority control bits of the Type C time base. The interrupt control and status bits for the
Type B time base are not used during 32-bit timer operation.
The following configuration settings assume Timer3 is a Type C time base and Timer2 is a Type B
time base:
void Timer23Int() org 0x22{ //Address in the interrupt vector table of timer3
IFS0 = 0; // Clear interrupt request
}
void main(){
TRISC = 0xFFFF; //PORTC<13>=1 T2CK is input pin
T3IF_bit = 1;
PR2 = 0xFFFF; //Interrupt peiod is 10 clocks
PR3 = 0xFFFF; //Total PR3/2=0*65536 + 10
T2CON = 0x800A; //Timer2/3 is synchronous counter of external pulses
while(1);
}
T2CON = 0x8002;
; The following code example will enable Timer2 interrupts, load the
; Timer3:Timer2 Period register and start the 32-bit timer module
; consisting of Timer3 and Timer2. When a 32-bit period match occurs
; the timer will simply roll over and continue counting.
; However, when at the falling edge of the Gate signal on [COLOR="#FF0000"]T2CK[/COLOR]
; an interrupt is generated, if enabled. The user must clear the
; Timer3 interrupt status flag in the software.
CLR T2CON ; Stops any 16/32-bit Timer2 operation
CLR T3CON ; Stops any 16-bit Timer3 operation
CLR TMR3 ; Clear contents of the Timer3 register
CLR TMR2 ; Clear contents of the Timer2 register
MOV #0xFFFF, w0 ; Load the Period Register3
MOV w0, PR3 ; with the value 0xFFFF
MOV w0, PR2 ; Load the Period Register2 with value 0xFFFF
BSET IPC1, #T3IP0 ; Setup Timer3 interrupt for
BCLR IPC1, #T3IP1 ; desired priority level
BCLR IPC1, #T3IP2 ; (this example assigns level 1 priority)
BCLR IFS0, #T3IF ; Clear the Timer3 interrupt status flag
BSET IEC0, #T3IE ; Enable Timer3 interrupts
MOV #0x804C, w0 ; Enable 32-bit Timer operation and
MOV w0, T2CON ; Start 32-bit timer in gated time
; accumulation mode.
; Example code for Timer3 ISR
__T3Interrupt:
BCLR IFS0, #T3IF ; Reset Timer3 interrupt flag
; User code goes here.
RETFIE
12.10.3 Asynchronous Counter Mode
Type B and Type C time bases do not support the Asynchronous External Clock mode.
Therefore, no 32-bit Asynchronous Counter mode is supported.
The 32-bit timer has the following modes:
• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
• Single 32-bit timer operation
• Single 32-bit synchronous counter
32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit period register PR3/PR2, then resets
to ‘0’ and continues.
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
Idle mode, the timer will stop incrementing unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU Idle mode.
Why in the code you posted T2CON and T3CON are cleared ? Where does it show configuration of T2CON and T3CON so that it is used as a 32 bit Synchronous Counter ? The mikroE page didn't tell why T3CON is not configured when using Timer2/3 as a 32 bit Synchronous Counter.
When configured for 32-bit operation, the control bits for the Type B time base control the operation
of the 32-bit timer. The control bits in the TxCON register for the Type C time base have no effect.
If anybody has used Timer2/3 of dsPIC30F as a 32 bit Synchronous Counter then please provide me an example code showing configuration of register and the ISR.
Code ASM - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ; The following code example will enable Timer2 interrupts, load ; the Timer3:Timer2 Period register and start the 32-bit timer ; module consisting of Timer3 and Timer2. ; When a 32-bit period match interrupt occurs, the user must clear ; the Timer3 interrupt status flag in the software. CLR T2CON ; Stops any 16/32-bit Timer2 operation CLR T3CON ; Stops any 16-bit Timer3 operation CLR TMR3 ; Clear contents of the Timer3 timer register CLR TMR2 ; Clear contents of the Timer2 timer register MOV #0xFFFF, w0 ; Load the Period Register3 MOV w0, PR3 ; with the value 0xFFFF MOV w0, PR2 ; Load the Period Register2 with value 0xFFFF BSET IPC1, #T3IP0 ; Setup Timer3 interrupt for BCLR IPC1, #T3IP1 ; desired priority level BCLR IPC1, #T3IP2 ; (this example assigns level 1 priority) BCLR IFS0, #T3IF ; Clear the Timer3 interrupt status flag BSET IEC0, #T3IE ; Enable Timer3 interrupts MOV #0x801A, w0 ; Enable 32-bit Timer operation and start MOV w0, T2CON ; 32-bit timer with prescaler settings at ; 1:8 and clock source set to external clock ; Example code for Timer3 ISR __T3Interrupt: BCLR IFS0, #T3IF ; Reset Timer3 interrupt flag ; User code goes here. RETFIE
freq = (((double)TMR3 * 65536.0) + (double)TMR2);
It worked but there is some problem. It displays correct value if 50 KHz is measured but displays wrong value if measured frequency is greater than 50 KHz. What is the problem ?
12.11 Reading and Writing into 32-bit Timers
In order for 32-bit read/write operations to be synchronized between the LSWord and MSWord
of the 32-bit timer, additional control logic and holding registers are utilized (see Figure 12-6).
Each Type C time base has a register called TMRxHLD, that is used when reading or writing the
timer register pair. The TMRxHLD registers are only used when their respective timers are
configured for 32-bit operation.
Assuming TMR3:TMR2 form a 32-bit timer pair; the user should first read the LSWord of the timer
value from the TMR2 register. The read of the LSWord will automatically transfer the contents of
TMR3 into the TMR3HLD register. The user can then read TMR3HLD to get the MSWord of the
timer value.
sTMR2 = TMR2;
sTMR3 = [COLOR="#FF0000"]TMR3HLD[/COLOR];
freq = ..... sTMR3.....sTMR2
To write a value to the TMR3:TMR2 register pair, the user should first write the MSWord to the
TMR3HLD register. When the LSWord of the timer value is written to TMR2, the contents of
TMR3HLD will automatically be transferred to the TMR3 register
After TMR2 becomes 0xFFFF, TMR3 starts incrementing. Right ? If yes, then if TMR2 is 0xFFFF and TMR3 is 0x0001 then result should be 65536. So, I have to add TMR3 and TMR2 values ?
Ok. I had to do this.
Code:freq = (((double)TMR3 * 65536.0) + (double)TMR2);
Now it is working fine.
What does TMR3HLD hold when TMR2 overflows ? 1 ? I mean TMR3 is copied into TMR3HLD ? How often or when the value is copied into it ?
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