manili
Member level 1
Why the result of Post-Synthesis Simulation is deferent from Behavioral Simulation ?
Hi all,
The following code is an I-Cache of a processor. The behavioral simulation shows no problem at all and the Cache just works fine. But when I do Post-Synthesis-Simulation, it looks like that the Vivado-Synthesizer did a huge optimization which ruined the whole system! The problem is "dat_o" which is the result of caching is always false and it looks like the simulator is running the if-else statements in parallel which is very odd to me!
Here is the code :
This is the result of Behavioral-Simulation :
This is the result of Post-Synthesis-Simulation :
Thank you.
Hi all,
The following code is an I-Cache of a processor. The behavioral simulation shows no problem at all and the Cache just works fine. But when I do Post-Synthesis-Simulation, it looks like that the Vivado-Synthesizer did a huge optimization which ruined the whole system! The problem is "dat_o" which is the result of caching is always false and it looks like the simulator is running the if-else statements in parallel which is very odd to me!
Here is the code :
Code:
`include "Global_Macros.v"
`define i_cache_size 512
module I_Cache(
rst_i, //Global reset signal
gbl_stl_i, //Global stall signal
rqst_i, //Received a request from core
extra_byte_cnt_i, //Signal to tell the cache number of EXTRA bytes prefetch unit used in prev process
adr_i, //Starting address of requested datas
ex_rdy_i, //A signal to notify cache, the requested data from main memory is fetched by MMU
ex_missed_dat_i, //Missed data is transfered through this line to the cache
ack_o, //Acknowledge signal to notify the core that the data missing is ready
dat_o, //A line to transfer requested instructions from cache to the core
ex_missed_adr_o //A line to specify address of missed data for the MMU
);
//Input signals :
input wire rst_i;
input wire gbl_stl_i;
input wire rqst_i;
input wire [1:0] extra_byte_cnt_i;
input wire [15:0] adr_i;
input wire ex_rdy_i;
input wire [7:0] ex_missed_dat_i;
//Output signals :
output reg ack_o;
output reg [23:0] dat_o;
output reg [15:0] ex_missed_adr_o;
//Internal registers :
reg [9:0] i;
reg [15:0] cache [0:`i_cache_size - 1]; //Valid[15]_Tag[14:8]_Data[7:0]
//Assignments :
//Blocks
always @(rst_i or rqst_i or ex_rdy_i)
begin
if(rst_i)
begin
ack_o = 1'h0;
dat_o = {3{`NOTHING}};
ex_missed_adr_o = 16'h0;
for(i = 0; i < `i_cache_size; i = i + 10'h1)
begin
cache[i][15] = 1'h0;
end
end
else if(rqst_i)
begin
ack_o = 1'h0;
if((extra_byte_cnt_i >= 2'h0) && (cache[adr_i[8:0] + 9'h0][15] != 1'h1 || cache[adr_i[8:0] + 9'h0][14:8] != adr_i[15:9]))
begin
//Request from main mem
if(ex_rdy_i)
begin
cache[adr_i[8:0] + 9'h0] = {1'h1, adr_i[15:9], ex_missed_dat_i};
end
else
begin
ex_missed_adr_o = adr_i + 9'h0;
end
end
else if((extra_byte_cnt_i >= 2'h1) && (cache[adr_i[8:0] + 9'h1][15] != 1'h1 || cache[adr_i[8:0] + 9'h1][14:8] != adr_i[15:9]))
begin
//Request from main mem
if(ex_rdy_i)
begin
cache[adr_i[8:0] + 9'h1] = {1'h1, adr_i[15:9], ex_missed_dat_i};
end
else
begin
ex_missed_adr_o = adr_i + 9'h1;
end
end
else if((extra_byte_cnt_i >= 2'h2) && (cache[adr_i[8:0] + 9'h2][15] != 1'h1 || cache[adr_i[8:0] + 9'h2][14:8] != adr_i[15:9]))
begin
//Request from main mem
if(ex_rdy_i)
begin
cache[adr_i[8:0] + 9'h2] = {1'h1, adr_i[15:9], ex_missed_dat_i};
end
else
begin
ex_missed_adr_o = adr_i + 9'h2;
end
end
else
begin
//Already cached, so return the result and turn off stall signal
case(extra_byte_cnt_i)
2'h0 :
begin
dat_o = {cache[adr_i[8:0] + 9'h0][7:0], dat_o[23:16], dat_o[15:8]};
end
2'h1 :
begin
dat_o = {cache[adr_i[8:0] + 9'h1][7:0], cache[adr_i[8:0] + 9'h0][7:0], dat_o[23:16]};
end
2'h2 :
begin
dat_o = {cache[adr_i[8:0] + 9'h2][7:0], cache[adr_i[8:0] + 9'h1][7:0], cache[adr_i[8:0] + 9'h0][7:0]};
end
default :
begin
dat_o = dat_o;
end
endcase
ack_o = 1'h1;
end
end
else
begin
ack_o = 1'h0;
dat_o = dat_o;
end
end
endmoduleThis is the result of Behavioral-Simulation :
This is the result of Post-Synthesis-Simulation :
Thank you.
.
