Why is the $monitor system task in Verilog defined inside an initial statement?

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Hi

Why is the $monitor system task always defined inside an initial statement? Why cannot the $monotor system task be defined as a independent statement outside the initial/always block?
 

verilog $monitor

Since this system task continuously monitors the values, it needs to be invoked only once and hence, it is typically invoked in the initial block since the initial block is also invoked only once during the length of the simulation.

However, it is not necessary that the $monitor statement HAS to be invoked through the initial block. You can invoke it in any procedural block (like always block). In fact, it may be invoked multiple times in conjunction with $monitoron and $monitoroff statements.
 

$monitor in verilog syntax

Hi madhavisai,

Is it just a coincidence that your reply matches word-to-word to my reply which I had given exactly a month before you? Please refer to the link below.


-Saurabh
 

$monitor verilog

yes , you should monitor the value always, so you should put it in the always module !
 

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