The gate lies on an insulated thin oxide layer (dielectric) above the substrate between the source and drain. The gate is effectively one side of a capacitor. This is the input impedance being referred to - the fact that the gate has no DC path to either source, drain or substrate.
The gate lies on an insulated thin oxide layer (dielectric) above the substrate between the source and drain. The gate is effectively one side of a capacitor. This is the input impedance being referred to - the fact that the gate has no DC path to either source, drain or substrate.
What about in case of JFET...?
There are no insulations in this case...
Is the High input impedance due to the reverse biased junctions at the gate...?
yes. it is. In case of BJT the input impedence is between emmiter and base and the junction is forward biased. Had the base been highly doped, the input impedence wiuld have been very low. With light doping in the base this impedance is increased.
in jfet the gate-channel junction is always reverse biased so the input impedance is high.if it was forward biased the input impedance bocomes very low.
in jfet the gate-channel junction is always reverse biased so the input impedance is high.if it was forward biased the input impedance bocomes very low.