why is that we take clock skew ast 20% of the clock period??

[vivekrajeev]

Hi
i do not understand how people arrived at the value that skew should be 20% of clock period. Could you please answer each question with number in detail. I would be so grateful to you

1. Also one more doubt does the area of the design influence the insertion delay ???

2. Also if i give a lesser skew value while building CTS will the cells sit much closely causing congestion and waste the remaining area??

3. Can i control the insertion delay of my entire design while building CTS?

4. i have a design that i want to operate at certain frequency how do I arrive at what skew no and insertion delay no i should have

Thanks
RLC

 

[soloktanjung]

Hi
i do not understand how people arrived at the value that skew should be 20% of clock period.

Who told you that? A senior design engineer? I understand that usually for a company you do already have specs for constraining the timing.

4. i have a design that i want to operate at certain frequency how do I arrive at what skew no and insertion delay no i should have

Why do we have to achieve a certain value for the clock skew? Why don't we force the tool to have zero clock skew?

Thanks.

 

[mail4idle2]

We use 20% uncertainity to consider all the factors which come into design after synthesis like Clock Skew, Process mismatch etc.