Why is STI done and how it impacts the stress?

[DS1988]

Why exactly is STI done ? What is the impact on the stress ?

 

[erikl]

Re: STI Stress

Why exactly is STI done ?

Device isolation, see here.

What is the impact on the stress ?

Below pls. find an overview paper about STI induced stress:

 

[DS1988]

Re: STI Stress

Hey thanks a lot but i have few more doubts......Doesnt the well itself provide an isolation? Why do v need to further do an STI ? Why is it shallow exactly ? Why cant it be deeper ?

 

[erikl]

Re: STI Stress

Doesnt the well itself provide an isolation? Why do v need to further do an STI ?

Well is operated as a reverse n+p junction, so passes strongly temperature-dependent leakage current, whereas STI is a true isolator (SiO2, glass), hence much less leakage. Moreover: less capacitance, and better separation from parasitic devices.

Why is it shallow exactly ? Why cant it be deeper ?

The simple try etch method produces trenches whose lateral dimensions are about the same as its vertical depth. So in order not to waste too much lateral silicon width/area STI usually is kept shallow. For HV circuits, however, also DTI (deep ...) technology exists (s.a. the a.m. Wikipedia article).
Some DRAM process also use laterally narrow but deep trenches for vertical charge storage, but this requires a more elaborate (= more costly) process.