Why is clock modelling necessary?

[pd_789]

Why do we need to do clock modelling (add uncertainity, latency, transition) though we overconstrain our design with 30% of clock?
Suppose if my design is designed for 100MHz i am applying 130MHz and synthesizing it(and it is passing) still why do i need to do clock modelling ?

 

[rca]

Well the clock description is also dependant of the design. If you have all clocks elements on the same edge, you don't care of the duty cycle.
It is always good to indicate a realistic rise & fall time, which will reduce the frequency.

In your case, it seems you have a lot of margin, the question is did you increased the area/power of your design by "over" constraining the clock frequency? Did you tried to draft a plot clock frequency versus area to check where is the break point?, and by this way you will know at which frequency the area is really impacted and then you add more margin with a "reduced" area impact.

 

[pd_789]

hi rca,

No change in area (for 100 or 130MHz) and i am not concerned about power numbers for now , can u plz tell me the significance of modelling clock though my design is workn wid higher frequencies?
I mean if my design is working at 130MHz without any timing violations , in real scenario it has to work at 100 MHz which it can easily do however the uncertainty or latency of the clock is? can you plz b clear?