sharanbr
Junior Member level 1

I am looking at a legacy design. The design accepts 2 clocks (of same frequency and from same source), one goes to core logic and other goes to SERDES block.
I am not sure why an indepdent clock is fed separately to SERDES while the same
core clock can be used. When I refered to design document, it says that this is for the PLL to have an independent clock referece ..
Any idea ?
I am not sure why an indepdent clock is fed separately to SERDES while the same
core clock can be used. When I refered to design document, it says that this is for the PLL to have an independent clock referece ..
Any idea ?