Re: About delay in MOS
So how do we improve the performance of the MOS...?
As you have mentioned increasing the MOS width with not alter the performance much...
That is not the conclusion to be drawn from my description of delay.
Below is an equation for the delay of a gate based on logical effort methodology.
Delay = a*(Cself/Cin) + b*(Cload/Cin)
= K + LE*fo
Cin= input capacitance of the driving gate
Cself = parasitic cap
Cload= load cap
a,b are constant for the specific type of gate topology (inv, nand, nor etc)
LE = logical effort of the gate and is constant for the specific topology.
Cself/Cin is more or less constant, since increasing gate size will increase both Cself as well as Cin and that effect cancels out.
Cload/Cin is called the electrical fanout of the gate.
If you want the delay through the gate to be small, you should make the gate bigger and that would reduce the fanout.
However, we have to keep in mind that there will be other gates that need to drive Cin. So, we cannot make the gate very big. You cannot size one gate in isolation but you should consider the full chain of logic or gates. Typically, there will be an optimum sizing solution. In the case of a chain of inverters driving a large load capacitance, the optimal electrical fanout is found to be between 3 and 4.
If you are interested, you should readup more on "logical effort". Its a very simplified but powerful way of looking at gate sizing.