Why Hold Violation is Fixed in Min Corner?

[hb_cancer]

hold violation

Hi,
I am new to Timing in Physical Design and I would like to know Why do we fix Hold Violations in the Min Corners{taking delay values from min corner of .lib's} and Setup Violations is fixed in Max Corner {ie reports & libs are used from Max Corner}. Please clarify on this... Thanks...

 

[koggestone]

fix hold site:edaboard.com

Generally

setup violations occur when Gate Delays are Big .Hence use max (Delay) Corner.
Hold Violations occur when Gate Delays are Small. Hence use Min (Delay) Corner.

 

[raju3295]

site:edaboard.com hold violation

hi,
Generally Hold violation comes if the combo logic become faster, so it is worth considerting the fast logic and fixing rather than with wrst delays

 

[hiral.kotak]

min and max corners for timing

Hi,

Hold time violations occur when the dat path is faster than the clock path. SO while checking the design for final tap out its better to consider the best delays (min delays) for data path and worst delays(max delays) for the clock path for hold analysis.
so, hold timings are checked in and fixed in min corner.

It may help you.

Thanks..

HAK..

 

[raki31]

hold analysis corners



we are fixing setup violation at MAX corner and hold at Min corner inorder to ensure that signal is within limits.....

 

[chaitubek]

min delay violation

Fixing the hold violations in the mincorner does not give the guarantee that it will fix the hold violations in the max corner also automatically, because the delays at different corners are not linear. we need to fix the hold violations in min and max corner.

Thanks,
Chaitanya.