For my project , my professor demanded that we use internal clock (no external reference or source clock) . And I did. But as it is internal , it changes from ff_corner to ss_corner.The changes is around 20% .Now I'm looking for a solution where I could synthesize the circuit which could maintain this range.From you explanation , I can say that ensuring such situation is not possible ?
Is there any way (like including this change as setup and hold uncertainty ) to handle this ?
If there is no other way, I have to solve the violations for a particular frequency. Then which frequency would be the safest bet ? tt_frequency (9MHz) or ff_frequency ( 11MHz) or ss_frequency (6.5MHz) ?
SideNote: As my professor demanded to include this clock inside the circuit, I could not use other clock here. It's kind of my design's requirement.
Thank you for your time