inter(adr) <= pin & pin & pin & pin;
found '2' definitions of operator "&", cannot determine exact overloaded matching definition for "&"
please show the whole code (especially the declarations) so we can see the context.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
----------------------------
entity neighbinter is
port( pin : in signed(7 downto 0);
clk : in std_logic;
pout: out signed(31 downto 0));
end neighbinter;
--------------------
architecture neighbinter_arch of neighbinter is
type int_type is array (0 to 63) of signed(31 downto 0);
type int1_type is array (0 to 63) of int_type;
signal inter : int1_type := (others => (others => "00000000000000000000000000000000"));
signal adr : integer range 0 to 4096 := 0 ;
begin
process(clk)
variable i,j : integer range 0 to 64 := 0 ;
variable k : integer range 0 to 4 := 0 ;
begin
if (clk'event and clk='1') then
if (adr < 4096) then
inter(adr) <= pin & pin & pin & pin;
adr <= adr+1;
end if;
if (adr /= 0) then
if (i < 64) then
if (k < 4) then
if (j < 64) then
pout <= inter(i)(j);
j := j+1;
if(j=64)then
k := k+1;j:=0;
if (k=4) then
k := 0; i:= i+1;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end neighbinter_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
----------------------------
entity neighbinter is
port( pin : in signed(7 downto 0);
clk : in std_logic;
pout: out signed(31 downto 0));
end neighbinter;
--------------------
architecture neighbinter_arch of neighbinter is
type int_type is array (0 to 63) of signed(31 downto 0);
type int1_type is array (0 to 63) of int_type;
signal inter : int1_type := (others => (others => "00000000000000000000000000000000"));
signal adr : integer range 0 to 4096 := 0 ;
begin
process(clk)
variable i,j,m,n : integer range 0 to 64 := 0 ;
variable k : integer range 0 to 4 := 0 ;
begin
if (clk'event and clk='1') then
if (m<64) then
if (n<64) then
inter(m)(n) <= pin & pin & pin & pin;
n := n+1;
if(n=64) then
n := 0; m := m+1;
end if;
end if;
end if;
if (i < 64) then
if (k < 4) then
if (j < 64) then
pout <= inter(i)(j);
j := j+1;
if(j=64)then
k := k+1;j:=0;
if (k=4) then
k := 0; i:= i+1;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end neighbinter_arch;
because when m is 63 it means that we write the whole matrix in ram and we want stop writting in RAM.There is still an error, because m never gets reset back to 0.
as i said before i write one image 64*64 in ram,i wanted to extend each pixel of each row(doing this by concatenation) and next i want to read each row four times(??this is the problem why i use all these counters and make it so complicated.).Why not just have a single addr counter that increaments from 0 to 4095?
i want to use this component in the main code, data is coming from the testbench i will write for the testbench.Where is the data for the ram coming from?
i didnt put write enable but because ofthere is no write enable on the interface so this just expects data from the start. Give this I dont really see the usefulness of this ram.
if (m<64) then
if (n<64) then
it doesnt have a reset because i just want to use it one time and the data is going to the next component (its the next function) i want to do after interpolation.Also, why doesnt i ever get reset? what is the data playing out to?
i want to repeat each of 64 row,can i do this with delay?Given this - why is this even a ram? the current design simply delays the input by a single clock cycle. Why not just put a register in there?
For actual implementation you would want to ensure this maps to efficient resources. This is 32bit * 4096 = 128kbit. This could map to 4 32k BRAMs or 128k registers. (or distributed ram in some amount in between).
The concatenation should be done on the read side of the ram, not the write side -- this cuts the ram size down by a factor of 4. The adr index should be limit to 0 to 4095, not 4096. The addressing may need to be limited to a single dimension (check synthesis tool documentation or results). This gets the ram size down to 1 BRAM, so further optimization is not required.
You would need some reset and read/write trigger/enable for this to be practical.
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