why have Offset voltage In Op amp in simulation spice?

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ohenri100

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Hi all,

I know about offset voltage (I think it present after layout or fabricate chip). But when I simulate by spice (only on spice, all MOS is matched). Why have the offset-voltage in my circuit in spice simulation?

Thank you.
 

Maybe your circuit is not symmetrical.
Maybe N channel device does not match P channel device.
 

You need to give a lot more detail of your problem. Do you have an unbalanced offset due to input bias current? Is this you own IC design (in which case this is in the wrong section)?

Keith
 

I think it is better if you show circuit and simulation results. Problem can be in input-referred offset from finite CMRR. It just as a version. Give a bite more.
 

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