Why ethernet is having separate clock in Spatran 3E starter kit

[moonnightingale]

I want to know that why Spatran 3E Fpga Starter kit is having seperate crystal of 25 MHZ for ethernet port. why it is not using onboard crystal or if atall it has to use 25 MHZ, if i make 25 MHZ from main clock by DCM, will my ethernet port work.

 

[Scrts]

Because the board is designed so. Ask Xilinx.
I am not sure if there is FPGA IO connected to PHY chip clock pin, but I am pretty sure it is not, so You will not be able to wire the clock signal from FPGA until You won't do some soldering stuff to connect those pins. Anyway, DCM is a bit crap, since generates a lot of jitter, also there are RX/TX clock pins to do data sync, so learn how to use them. Having Your generated clock in the PHY would be OK, if there would be no delays inside the chip which could be a great PITA for correct design...

 

[permute]

yes, the PHY will provide a TX Clock and an RX Clock. The PCB doesn't have any connection to the PHY's clk_in port from the FPGA. The onboard xtal for the FPGA looks to be 50MHz, which is not 25MHz. This allows the user to change the onboard xtal to a different device while allowing the ethernet port to function -- changing the system clock doesn't affect the PHY's independent xtal.

 

[moonnightingale]

Is there any FPGA kit in which Ethernet uses clock of the board.??Any experience on that