why does NMOS pass a strong logic 0 and a weak logic 1

[Shanthanayaki]

pmos weak 0

Hello everybody ,
Can anyone tell me, why NMOS pass a strong logic 0 and a weak logic 1 ?.
Vice versa why PMOS pass a strong logic 1 and a weak logic 0 ?.
Thanks,
Shantha

 

[IanP]

nmos pass a “strong” 0 but a “weak” 1

... in an NMOS process, logic circuitry is often constructed using a weak transistor that is always on and one or more strong transistors that are switched on and off. In NMOS the weak transistor is used to generate a high output voltage level or 1 when the strong transistors are turned off. When a strong transistor turns on it overwhelms the weak transistor and forces the output voltage low, which represents a 0.

Quoted from:
https://www.realworldtech.com/page.cfm?ArticleID=RWT050802020022&p=3

Regards,
IanP

 

[Shanthanayaki]

nmos weak 1

... in an NMOS process, logic circuitry is often constructed using a weak transistor that is always on and one or more strong transistors that are switched on and off. In NMOS the weak transistor is used to generate a high output voltage level or 1 when the strong transistors are turned off. When a strong transistor turns on it overwhelms the weak transistor and forces the output voltage low, which represents a 0.

Quoted from:
http://www.realworldtech.com/page.cfm?ArticleID=RWT050802020022&p=3

Regards,
IanP

Hi,
Thanks. Appreciate the help
Shantha

 

[gharuda]

can both pmos and nmos pass good 1 and good 0

hi

the page just explains about the technology used, intially PMos tech, later Nmos tech was in use and currently Cmos tech is being in use.

but still i didnt get the picture how and why does nmos pass good 0 and bad logic 1
and pmos pass good 1 and bad logic 0.
However still the tranistor pass good 0 and considerable 1 in nmos when used as a pass tranistor - that of threshold voltage.(turn on voltage)

Infact this may due to the majaority carries holes and electrons in p and n type.
like in any circuit two types current flows one is coventional and other is electon drift current. as convential current flows from +ve terminal to -ve terminal and the electron current from -ve to positive.

if we consider a Cmos inveter when the input is logic 0 the pmos tranistor turns on. source of pmos is more positive than the drain terminal, as the majaority carrier is holes whichs consitutes conventional current flows from source which more +ve than drain and flow of conventianal current is from +ve terminal to -ve terminal. thus the output which is drain is pull high faster compared to nmos . (pmos switching action is faster)

when the input is logic 1 the nmos tranistor turns on. source of nmos is more -ve than the drain terminal, as the majaority carrier is electrons in nmos .electon current flows from source to drian .thus pulling down the output drain to low.

switching action of tranistor plays a important role.

 

[kuo]

vgs of nmos

For NMOS to pass 0, as long as Vgs> Vt, NMOS can trun on. It is strong to pass 0.
For NMOS to pass 1, it needs Vgs > Vt to turn on. So it weak to pass 1.
For PMOS to pass 1, the Vg is easy to turn on and pass whole "1"...

So it has PMOS and NMOS to make transmit gate instead of one transistor alone.
It can pass 1 and 0 in good condition.

 

[shyamsundar]

eplanation of working of n-mos

Hello the explanation regarding the Weak logic 1 by NMOS and logic 0 by PMOS, I felt is inadequate. Can anyone elighten on this in detail??
This is one of the major interview questions in physical Design VLSI and MOS Circuit analysis.

Thanks in advance

 

[ninge]

nmos strong zero and weak one

Hi All,

please go through the attachment page no 7 and 8 which discuss about the topic...
I hope this will help..

Regards,
Ninge

 

[salma shabayek]

attached is a lecture explaining it very wel with examples

 

[suze]

thanx really good attachment , i searched a lot for such convincing answer.finally got it in book by (Cmos vlsi design) neil weste page no. 66--- pass transistor char.

 

[trailokyanathITBHU]

NMOS need +Vt for on,when gate voltage is 1(Vdd) and source voltage applied is 0, than Vgs(GATE to SOURCE) become Vg-Vs=Vdd-0=Vdd which is greater than Vt so it allow strong 0 and output is 0.If source voltage applied is 1(Vdd),than Vgs=Vg-Vs=Vdd-Vdd=0 so NMOS not allow 1 so NOMS act as open switch. But if source voltage is Vdd-Vt ,than
Vgs=Vg-Vs
=Vdd-(Vdd-Vt)
=Vt......................which on the NMOS so output is Vdd-Vt
which is weak 1
if we apply Vdd≥Vs>(Vdd-Vt) input is not pass to output.

 

[bhishmar]

if we apply Vdd≥Vs>(Vdd-Vt) input is not pass to output.

All of trailokyanath last post is valid & the only correct explanation of the original query- ie. except for his last line quoted above. All other previous posts quote articles, which simply re-state the question.

But the quoted last line seems erroneous, since it violates the boundary condition, from commonsense point of view. (also he uses Vs to refer to Vi).
If input voltage (Vi) exceeds (Vdd-Vt), it says input is not passed to output. In reality output will not be zero volts then, instead it will be= Vdd-Vt.

This is also because the output capacitance at the load charges-up from zero onwards, till the output reaches the value = (Vdd-Vt), at which point the channel gets cut-off (due to Vgs < Vt), at that instant.

Ref1: **broken link removed**
Ref2: **broken link removed**

 

[vishnu.mthss]

Hi all

What i could make out is as follows:
When the NMOS needs to pull down something or when the PMOS needs to pull up something, they can do so without Vds affecting the load.
ie, they can pass a strong 0/1 as the case may be.
But, when they try to do the reverse, some drop will be there in the form of Vds, so the output is not strong.

Please correct me if i'm wrong.
Regards.

 

[srihari465]

Hi,

While taking simple inverter circuit the NMOS will be on when only, we will give the logic 1 to its input , at the same time PMOS will be in off state so,the NMOS
will passes strong '0's and weak '1's.Vice versa for PMOS also........






THANKS & REGARDS
SREEHARI...