Why does Design Compiler increase area when using a generate statement with condition

[dw_man]

I am using a generate statement to instantiate a module which is causing an unexplained increase in are after DC synthesis.

I am using Verilog

The first snippet of code gives me a certain area

generate
   module_name instance name
endgenerate

I also get the same area if I don't use the generate statement.

When I use the second snippet of code, I get an increased area

generate
   if (1) begin
      module_name instance name
   end
endgenerate

Even if I use case statements with parameters inside the generate, I am getting the exact same number as the second snippet of code.

Is there a particular reason for this? Shouldn't this code be elaborated the same way?