Why do you specify input and output delays when doing synthesis in Synopsys DC?

[davyzhu]

Hi all,

I was asked in interview, but I am not familiar with DC
"While synthesis of a design using synopsys design compiler, why do you specify input and output delays?"

Is these delay related to Tsu, Thd, and Tcq?

Any suggestions will be appreciated!
Best regards,
Davy

 

[hawk_chenbo]

synopsys input delay output

Tsu, Thd, and Tcq are characteristics about timing logic cells. They depend on the kind of the cells.
While input and output delay setted are to be consider external logic delay for input ports and logic delay to external logic for output ports.

 

[anjali]

Re: Synopsys DC problem?

input & output delays are used to model the environment of that module.

one module's input port will be an output port of other module in an SOC environment. so input for that module will not be ready at the clk edge. ie the input arrival takes some time to reach the input port. that delay is modelled using the constraint "set_input_delay" in DC.

similarly "set_output_delay".

 

[ami]

Re: Synopsys DC problem?

input and output delay in DC are set as design constraint. a normal input/output of a design should have its reference clock, DC use input/output delay to calculate timing of input/output with this clock (setup/hold..)

 

[silencer3]

Synopsys DC problem?

Input delay: to tell tool that the time for First FF in design is CLK_Period - input delay. means the logic synthesis and placement is done such that the first FF gets the input with in that time, to satisfy the external input delay.

Output_delay : to tell the tool that the last flop to output delay should be the specified one to satisfy the external environment setup and hold times.

These are TOOOOO important for ASIC and as well FPGA to work correctly.

 

[salma ali bakr]

Re: Synopsys DC problem?

The input and output delays are design constraints, or optimization constraints...
The input delay is the amount of time that the signal is required after the clock edge...
Similarly, the output delay is the amount of time the signal is required before the clock edge...where its maximum value is the longest path delay to that register + setup time, and its minimum point is the short path delay to that register - hold time

 

[nine8]

Synopsys DC problem?

they are both the margin for the external circuit

 

[archillios]

Synopsys DC problem?

Input delay or output delay is set as constraints, then compiler will know how to optimizie the logic near block pins. They represent timing environment of the block.

 

[vlsichipdesigner]

Re: Synopsys DC problem?

hi,


Request you to check the mentioned link which will help to understand the concepts better.

https://www.vlsichipdesign.com/static_timing_analysis.html

happy designing,

chip designing made easy
https://www.vlsichipdesign.com