# Why Do We Use PLL in Digital Circuits?

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#### ReubenMijares

##### Newbie level 6
In most ICs I encounter, PLLs are present. But I don't know actually what's the use of it. Some registers are associated with it which you need to program. May I know what's the use of this PLL and why are the registers need to be configured?

I know how PLL works. It takes 2 input frequencies, one is from a crystal oscillator which is stable, while the other one is from a VCO. The phase difference is compared to create a signal with a stable phase/frequency.. What I don't understand are the following:

1.) The crystal oscillator is already stable. Why not just use that signal for the clock? No need to compare 2 signals, right?
2.) What are its used for digital circuits? Is this to create a stable clock?
3.) Can you explain how programming the registers can alter the behavior of the PLL?

Regards,
Reuben

#### KlausST

##### Super Moderator
Staff member
Hi,

Within a PLL there usually are two frequency dividers.
* one is in the input side (let's call it "d")
* one is in the feedback loop (let's call it "m")

Because one is in the feedback loop, it acts as a "multiplier" for the output frequency.

So you get a very flexible adjustment of the output frequency. It may be lower, equal or higher than the fixed input frequency.

F_out = f_in * m / d

In reality there are limitations because of VCO range limitations and loop stability problems. Therefore not all 256 x 256 combinations are possible.

Imagine you have 1.00MHz input frequency m= 41 and d= 40.
This results in 1.025 MHz
M=42, d=40 results in 1.050MHz
M=42, d=41 results in 1.02439MHz

Klaus

#### ReubenMijares

##### Newbie level 6
Hi KlauST,

So this means that the reason why we use PLL is because the input frequency is fixed which limits the application to that certain frequency only. Thus, with the use of PLL, we can derive different frequencies based from the input frequency. Is this correct?

Then the registers are the ones that specify the value of M and D? Am I getting your point?

I think this post is more related to ASIC Design than here in Digital Communications.

Regards,
Reuben

#### betwixt

##### Super Moderator
Staff member
Correct - but you are missing one important point, the new frequency is selected by the division ratio but is still locked to the reference clock. The PLL allows selection of different frequencies while retaining the stability of the timing source.

Yes, the M and D mentioned by Klaus are numeric values programmed into the registers so you can adjust the VCO frequency by writing new values to them. This is in essence how synthesized tuning works.

Brian.

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