# Why do we not consider Cgd4 in this differential pair?

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#### mince

##### Member level 5
In the differential pair in the picture, the second pole is equal to gm3/Cx where Cx is the total capacitance in node X to ground. It is approximated to be Cgs3+Cgs4. Why do we not consider Cgd4? For small lengths, wont the miller effect from the gate to drain of M4 cause this capacitance to be on the order of the gate-source capacitances?

#### nandu_r

##### Member level 1
Re: Diff pair question

cgd capacitance is the overlap capacitance, and for smaller length , the gain is not much, so that part is usualy neglected

#### willyboy19

##### Full Member level 3
Re: Diff pair question

Cgd4 does not need to be accounted for the pole at Cgs3 and Cgs4, this is because a pole-zero doublet happens before the Cgd4 Miller cap can take effect.

#### philipwang

##### Advanced Member level 4
Re: Diff pair question

Actually we negleted these capacitance:
Cgb3, Cgd1, Cgb1, Cgd4, 'b' indicates bulk.

Bg,

mince said:
In the differential pair in the picture, the second pole is equal to gm3/Cx where Cx is the total capacitance in node X to ground. It is approximated to be Cgs3+Cgs4. Why do we not consider Cgd4? For small lengths, wont the miller effect from the gate to drain of M4 cause this capacitance to be on the order of the gate-source capacitances?

#### rockycheng

##### Member level 5
Re: Diff pair question

mince said:
Cx is the total capacitance in node X to ground.

I think you have answered the question by yourself. Cgd4 is not connected to ac ground. :|

#### mince

##### Member level 5
Re: Diff pair question

rockycheng said:
mince said:
Cx is the total capacitance in node X to ground.

I think you have answered the question by yourself. Cgd4 is not connected to ac ground. :|

But due to the miller effect, there is an equivalent capacitance between the gate and AC ground that is equal to (1+gm4*ro4||ro2)*Cgd4. Since Cgs is equal to 2/3*WLCox and Cgd=Ld*W*Cox, if Ld*(1+gm4*ro4||ro2) is close to or bigger than L, then the gate drain capacitance can affect our second pole, or am I doing the analysis wrong?

#### rockycheng

##### Member level 5
Diff pair question

Yes you are right about the miller capacitance. The problem is that you are considering the Cx, which is the total capacitance from node X to the ac ground, as you said. Although Cgd4 is large duo to the miller effect, this value should be parallel with (Cdb2+Cdb4). The result is that it is negligible.

#### fendy

##### Junior Member level 3
Re: Diff pair question

The Miller effect is Z1=Z/[1-(-Av)].
The gain is so huge,so the Cgd4 & Cgd1 can be neglected.
If the gain enough small,the Cgd4 & Cgd1 cann't be neglected.
FYI

#### wanily1983

##### Member level 5
Diff pair question

in prof.RAZAVI's book, Cx is include the Cgd4, when all transistor work in saturation region, Cgd is very very small ,which is Cov*w, while Cgs is 2/3*W*Leff*Cox. even if the gain is large,the effect of Cgd can be neglected.

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