shiv_emf
Advanced Member level 2
Hello
Before sending netlist or GDSII file to Fab..
Design is implemented on FPGA board...... if this is true then
y are FPGA run on slower clocks than ASIC?
When Fpga cannot verify timing of design ....... wht cud be possible reason to implement design on FPGA?
thanks
Shiv
Before sending netlist or GDSII file to Fab..
Design is implemented on FPGA board...... if this is true then
y are FPGA run on slower clocks than ASIC?
When Fpga cannot verify timing of design ....... wht cud be possible reason to implement design on FPGA?
thanks
Shiv