Why do we need a reset input for DFT scan testing

[rmohan_y]

I am new to the DFT methodology and trying to understand the basic concepts behind the scan. I have the following doubts. Can somebody help me?
1) I understand that the reset is required during functional mode to initialize the flops with required values after power up . There is no such requirement for DFT scan as we don’t depend on the reset values of flops as we shift in the patterns and shift out the captured values. Why do we need reset input for scan?
2)What kind of manufacturing defects(like stuck-at fault, slow-to rise/fall issues present in gates) are possible in reset network?
3) I saw that i_dfx_fscan_rstbypen is used for for selecting the reset(i_dfx_fscan_byprst_b) during scan. Can i use i_dfx_fscan_mode instead, so that we can save one extra input?

 

[weetabixharry]

Please define DFT. Its most common meaning in electronic engineering is Discrete Fourier Transform.

 

[macein]

In semiconductor industry, DFT stands for Design For Testability. It is a step in the VLSI design Flow. By using the DFT methodology the chip is tested for manufacturing faults (not functional faults, which are taken care by verification engineers). Manufacturing faults include stuck-at 0 (ground/VSS), stuck-at 1(Power/VDD), opens, shorts, transition faults(0->1, 1->0), memory faults (viz. address decoded faults, coupling faults etc.) and various other faults.
Scan chains are stitched using the Flip Flops present in the design, which is used for testing the combinatorial logic of the chip. For testing the memories, Built in Self Test (BIST) is performed. Automatic Test Pattern Generation (ATPG) is a major step in this process where patterns are generated, which are simulated (pattern validation) to test for possible causes of failure of the chip.
Generally a test coverage of more than 98%-99% is required for digital chips, only after which a green signal is given to fabricate the chips. Once the chips are manufactured, the ATE engineer will run the test-patterns on the tester to check the sample chip for any possible failure and debug the issue/cause. This is called as silicon validation.

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@rmohan_y: In DFT, the reset/set pin should be directly controllable from the input. The main aim of DFT is to provide control-ability and observability to the design. In a good design one tries to achieve control-ability of the inputs by constraining the primary inputs and all the outputs should be observable at the primary outputs.
Ans1) The rest pin of the Flip-Flops (FFs) used in scan chain should remain in deactivated/non-asserted state when one is loading and unloading the patterns. In order to achieve this, the reset/set pin should be constrained to the inactive state during loading/unloading. Thus, it becomes necessary.
For example: if 3 FFs are present, all the three's reset should be inactive during shifting operation.

Ans2) Manufacturing defects like stuck-at 0, stuck-at 1 fall under stuck-at faults category; slow-to-rise and slow-to-fall come under delay fault model. Also there is transition faults, in which the node can toggle from 0 to 1 but not 1 to 0 or vice-versa. For memories, we have state-coupling faults, stuck-at faults, tranisition faults, address decoder faults. Other faults are tied, redundant, blocked, unused faults.

Ans3) Not sure about this one, but will try to provide an analogy. According to me the reset needs to be dedicated.
For example, The scan-mode and scan-enable are two different signals. During the test operation of the chip, scan mode will always remain high(means active), but scan-enable will toggle(it will be 1 during scan chain loading and unloading, while it will be 0 during the capture cycle in the test-operation mode.

 

[rca]

Well controlling the reset pin of the flop is only to increased the scan coverage.
if there is not enough pads for that, the reset should in the inactive state to be able to shift in/out the scan chains.

 

[kornukhin]

The main reason why test reset should be used is that you will not cover pathes to SET/RESET pins of the DFF, as functional reset should be inactive during scan test. Thus any defect on reset path (except stuck-at which will prevent scan chain from shifting) will not be detected.

Generally you need only 1 extra pin - 'test_mode' for DFT. Any other can be multiplexed. (In some cases internally generated test_mode can be used, but this technique is far more complex).

 

[ranger01]

Just to add to the above answers, a reset signal can also be internally generated in the design, during scan shift this reset signal can get activated and reset a particular flop in the chain, if this happens then all the flops proceeding to the reset flop will receive reset value and not the intended input pattern. Hence a flop which needs to be included in the scan chain must have its reset completely controlled in the DFT mode. With the complete control-ability the reset will be held inactive during scan shift and during capture the control should be given to the functional path.