oldhat
Newbie
I'm a long time user of the Verilog, and do not have a lot of experience in VHDL.
So I have a question: why is it advantageous to have a component in VHDL?
Basically, you need to write the same thing twice - as an entity and as a component?
So I have a question: why is it advantageous to have a component in VHDL?
Basically, you need to write the same thing twice - as an entity and as a component?