# [SOLVED]Why do we need a component in VHDL (why having entity and architecture is not enough?

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#### oldhat

##### Newbie
I'm a long time user of the Verilog, and do not have a lot of experience in VHDL.
So I have a question: why is it advantageous to have a component in VHDL?
Basically, you need to write the same thing twice - as an entity and as a component?

#### alexan_e

Actually you can imagine it as a hardware component with a specific behavior internally and all that is exposed are the inputs/outputs.
To use its functionality in your implementation you just need a socket (port map) in which it fits, you don't need to rewrite the code of that component.

see for example

Alex

#### oldhat

##### Newbie
But this is perfectly solved by entity/architecture pair: you define your interface in the entity and have different implementations in different architectures.

#### FvM

##### Super Moderator
Staff member
You can see the component definition as a prototype to tell the compiler about the exact type of all interface signals. It is however not necessarily needed, you can instantiate components compiled to a project library by explicitely naming it. In this case, no previous component definition in the architecture is required.

Code:
instead of
component_instance: component_name
port map (  );

you can write

component_instance: entity work.component_name
port map (  );

But language syntax is determined by convention and legacy to a large amount. In so far it's of limited purpose to ask "why is it so?",

digi

### digi

Points: 2

#### oldhat

##### Newbie
The purpose of my question is to understand the language better and may be to find it useful in some cases. So far I see having both entity and component
as absolutely useless, just more typing and elaboration errors that entity is not bound. If it it's only matter of syntax, why not to have a switch to allow compilation/elaboration without having a component. Basically, you will instantiate an instance of an entity, instead of a component. By the way, some articles (I think mistakenly) mention instantiating of entities.

#### FvM

##### Super Moderator
Staff member
I think, the said syntax (using a full entity name) should basically do what you want. Explicite component declaration is still required for mixed language, when instantiating Verilog modules. As a disadvantage, the instantiated components must me explicitely included to the project. With component declarations, they are automatically imported if the VHDL file name is identical to the component name.

oldhat

### oldhat

Points: 2

#### Aritra17

##### Member level 1
you need to define the component just to give the ports of the particular module you will be using in that program.
the smaller blocks grow up into bigger blocks
you need to define the ports of the smaller blocks for the bigger block similarly like netlist in tanner eda software

#### srizbf

consider a nand gate for this discussion.

you are giving entity and architecture of nand gate.
by entity you are giving about its input and output.
by architecture you are giving its function (what is inside).

but what you are giving is about a nand gate.

if your circuit has many nand gates , you know that you have given the behaviour of nand gate with entity-architecure pair.

but that is about a nandgate , in general.
if the circuit has gate N! , N2 ... as many gates , then you are giving them as 'component' saying that this is N1 , whose behaviour is already given as entity-architecture pair.

this is called as 'insantiation ' , ie, you are making an instance general nand gate as N1.

think of your schematic libray containg general nand symbols.
from library , if you place the symbol on a sheet , it is a nand but you taking an instance of the symbol and give it a name as N1.

so , entity-arch pair is eqt to lbrary .
'component' is one instance of the library.

i hope you are clear.

#### oldhat

##### Newbie
I think, the said syntax (using a full entity name) should basically do what you want. Explicite component declaration is still required for mixed language, when instantiating Verilog modules. As a disadvantage, the instantiated components must me explicitely included to the project. With component declarations, they are automatically imported if the VHDL file name is identical to the component name.

Thank you for this point (using a full entry name). I will try it.

Browsing on the net, I found one useful example of components. In board design, a component can represent a socket on the board, an entity is a chip package where chip interface must match the socket interface, and architecture is an implementation of a chip.
So in configuration you can specify what particular socket you are using (can be different kind of sockets -different manufacturer for example), and entity/architecture pair will specify what chip you will plug in (entity - different speed, different manufacturer) and what model(architecture) of a chip of a particular manufacturer..

---------- Post added at 11:34 ---------- Previous post was at 11:25 ----------

consider a nand gate for this discussion.

you are giving entity and architecture of nand gate.
by entity you are giving about its input and output.
by architecture you are giving its function (what is inside).

but what you are giving is about a nand gate.

if your circuit has many nand gates , you know that you have given the behaviour of nand gate with entity-architecure pair.

but that is about a nandgate , in general.
if the circuit has gate N! , N2 ... as many gates , then you are giving them as 'component' saying that this is N1 , whose behaviour is already given as entity-architecture pair.

this is called as 'insantiation ' , ie, you are making an instance general nand gate as N1.

think of your schematic libray containg general nand symbols.
from library , if you place the symbol on a sheet , it is a nand but you taking an instance of the symbol and give it a name as N1.

so , entity-arch pair is eqt to lbrary .
'component' is one instance of the library.

i hope you are clear.

As I said before, you can instantiate an entity, instead of component. This is a syntax issue.

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