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with NDR you mean Non-default-Rule as routing constraints?, if it is that, the leaf net will connect the pin cell and need to be on M1 (generally), and on inside the std cell there are in general some M1 blockage, that never allowed (enough space) to respect this NDR.
To apply NDR on clock nets is to reduce crosstalk effect.
TSMC recommends to apply double spacing and double width on all clock nets.
P&R tool will automatically fix DRC violations caused by NDR on M1, or designer could define NDR from M2 directly.