Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why do MIPS instructions sw and lw need base and offset?

Status
Not open for further replies.

matrixofdynamism

Advanced Member level 2
Joined
Apr 17, 2011
Messages
593
Helped
24
Reputation
48
Reaction score
23
Trophy points
1,298
Activity points
7,681
This is about the load word and store word instructions in MIPS. The MIPS load word instruction looks like this: lw $rt, offset($rs) and the sw instructions is simillar. In both cases we have a word at a 32 bit address location in main memory that we want to load/store. So we first store a base address into a resgister $rs and add an offset to it when sw or lw is called. The value in register $rs is 32 bits anyway right!? And the offset is a 16 bit signed number.

Why don't we just have use the single 32 bit value in $rs rather than bother about base and offset addresses and adding them. Does this not cause confusion?
 

it will not cause any confusion.
it is a feature given for certain environment apps.
for example , if rs is loaded with one 32 bit number ,
the you can access the nearby locations within the +/-16k region., by changing the offset alone.

that is , you are referring the address from base, + or - some distance from base.

good for retrieving a set of constants or database of the same group by using the offset addressing technique.
 

What does MIPS need funct as field in instructions for arithmatic operations?

The opcode for the MIPS 32 bit processor has more than enough bits to cover each type of arithmatic operation. Why then is the funct field used in the instructions?
 
Last edited by a moderator:

What is the difference between li, la and lw instructions in MIPS

load immediate loads an actual value into a register location, it can be compared with the x86 mov instruction. Then load word simply loads the contents of memory location into general purpose register. What why would one need to use the la instruction which loads an address? What is its application?

Also, correct me if I am wrong, I think that the "general purpose registers" and the memory are part of a continuous address space from the perspective of the MIPS. If this is true than why can't one simply refer to things in the memory rather than first load into into the general purpose register and then use the value from the register in an instruction?
 
Last edited by a moderator:

Re: What is the difference between li, la and lw instructions in MIPS

All processing of data is done by the microprocessor. Values stored in RAM has to be brought to general purpose registers of microprocessor and then processed. General purpose registers are faster compared to cache and RAM. To get value stored in RAM location x the microprocessor has to be provided the address of the memory location. This is direct addressing. In indirect addressing the address of the memory location whose value has to be read is loaded into a register and then dereferenced. This loads the value stored at that memory location in RAM to microprocessor's register.
 

The following things are still not clear to me:

(1) are the memory and register file part of the same continuous memory space? If so, then it means that the register file occupies the first 32 addresses in this space and the memory occupies the rest?

(2) what is the use of la instruction which stands for load address, don't we use lw and then use this loaded value as an address in a later instruction?

(3) when the opcode field is fully capable of being different for each R-type instruction, why then do we need a funct field? it appears redundant to me.

(4) the instruction memory stores 32 bit words. Thus each successive address should refer to the next 32 bit word rather than the next byte. Why then do we add 4 to get the next value from the program counter and not 1?

(5) For jump and branch instructions the immediate address value is first shift left by 2 before it is used with the program counter. Why? What would happen if this was not done?

(6) the branch and jump instructions contain address in them. The branch instruction uses a stored 32 bit value with an offset for the address e.g beq rs, imm(rt) where address is calculated as 32 bit rt + 16 bit imm. This way it can access all locations accessible using a 32 bit address. However, the jump instruction only has a 26 bit address as immediate within the instruction. This is connected to 4 most significant bits from the program counter value incremeted by 4. Does this mean that the jump instruction cannot access all the 32 bit address locations? What is the logic of joining the output of the program counter on top of the 26 bit immediate value from the jump instruction?

- - - Updated - - -

(7) If a single branch or jump instruction is not able to access all of the 32 bit memory in a single instruction, what are the different ways to mitigate this limitation?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top