[SOLVED] why do I read junk value in my ILA waveform

[sreevenkjan]

Hi guys,

I am not able to read the desired output of a signal from the fpga in the ILA waveform.I have connected one of the probe to the signal.I am reading junk values.Could you tell me what could be the reason why I am getting junk values for a 14 bit wide signal..Its showing as "3FFF" as in all the bit values are high.

Thanks in advance

 

[TrickyDicky]

Then I assume the input to the ILA is reading "3FFF". The problem will be further upstream. The ILA isnt broken.

 

[sreevenkjan]

Then I assume the input to the ILA is reading "3FFF". The problem will be further upstream. The ILA isnt broken.

Hi,

I do not understand what you mean by upstream..In simulation my output is x3009..
What do you mean by ILA is not broken??

 

[TrickyDicky]

Basically, the problem will be in the logic connected to the ILA. There is no problem with the ILA.

Are the inputs on hardware the same as in simulation? is something stuck in a reset state? has logic been removed?

 

[sreevenkjan]

Basically, the problem will be in the logic connected to the ILA. There is no problem with the ILA.

Are the inputs on hardware the same as in simulation? is something stuck in a reset state? has logic been removed?

yes i have used the same inputs and i have connected the signal which i need to monitor to the probe of the ila,but it shows me a junk value.i have used a reset_n signal which when active will not reset the process.No logic has been removed.

when count_output =>
                count1 <= counter_array(conv_integer(count_loop));
                if count1 > prev_count then
                   biggest_count <= count1;
                   count_number <= count_loop - "1";
                else
                   biggest_count <= prev_count;
                end if;
                prev_count := biggest_count;
                count_loop <= count_loop + "1";
                --data_out <= label_pixel_start(conv_integer(count_number)) & label_pixel_end(conv_integer(count_number));
                if count_loop = label_number then
                   row_addr <= "000000000";
                   count_loop <= "00000000";
                   biggest_count <= "00000000000000";
                  --state <= addr_increment;
                --else
                   state <= count_output;
                end if;
           end case;

the code which has the state machine count output will return the value of signal biggest count connected to the ila probe.However in the pic attached you can see some junk values.
my output obtained from simulation is of value 12297.

 

[TrickyDicky]

The only answer is - there is something wrong with your logic. There is a missmatch between what you're simulating, and what is implemented. Usually this is due to poor quality testing, with test cases that do not match the real system, or poor code that does not produce the logic as expected.

You say you have to same inputs: have you checked on the ILA they are being fed into the design the same way they are in the simulation?

Have you checked the RTL diagram? does it produce the logic you expected it to? have you got the pinout connected correctly?

There is not alot we can do to help except review your code. The code you posted is just a snippet so I have no idea what it's trying to do in context.

So you need to take a step back - the "junk value" on the ILA tells you something is wrong. But just posting "my design isnt working", doesnt help unless you can pinpoint where its not working and provide us with details.

 

[pbernardi]

As TrickyDicky pointed out, there is a mismacth between your simulation and what runs on FPGA. A commom difference between simulations and real world is the clock, so I would suggest you to check if your clocks are working in your design.

You could route your clocks to external pins and measure it, just to be sure they are active.

 

[sreevenkjan]

well my system uses only one clock and in simulation i just set the value of this clock by assigning the period that is 100MHz or 10ns...I am using 3 arrays as look up tables from where i store my values and use it as data table for indexing...well my system has only one input that is the clock which i have assigned to 100Mhz...do i need to use BRAMs instead of using arrays??...

 

[TrickyDicky]

the arrays should have mapped to BRAMs - hence why I said you should be checking the RTL diagram to see if the hardware is as you expected. You also get a quick check if anything has been removed.

When are you capturing ILA data? does the system reset itself to create a neverending stream of data? are you sure you're not just capturing when data generation has finished?

Why not try connecting the ILA to the input data to ensure that is being generated correctly. I assume that, if you have no inputs other than a clock, source data comes from a ROM - has the compiler picked up the file to initialise the ROM correctly? are the address generators generating the read address correctly?

Basically, there is lots for you to look at. If you had a system where you could input and output data to a PC, you could input any data, read the output and use the ILA to debug the design (but the ILA would always be a last resort - you revert back to simulation wherever possible).

 

[sreevenkjan]

the arrays should have mapped to BRAMs - hence why I said you should be checking the RTL diagram to see if the hardware is as you expected. You also get a quick check if anything has been removed.

When are you capturing ILA data? does the system reset itself to create a neverending stream of data? are you sure you're not just capturing when data generation has finished?

Why not try connecting the ILA to the input data to ensure that is being generated correctly. I assume that, if you have no inputs other than a clock, source data comes from a ROM - has the compiler picked up the file to initialise the ROM correctly? are the address generators generating the read address correctly?

Basically, there is lots for you to look at. If you had a system where you could input and output data to a PC, you could input any data, read the output and use the ILA to debug the design (but the ILA would always be a last resort - you revert back to simulation wherever possible).

hi tricky,

i had a look at the rtl schematic no logic's are rmoved.I also checked the report whch does not give any errors or any problem.

yes i am recalling the state machine after i get the output.so the process is repeated as a loop.the ila is showing the filtered output so there is no issue with the filtered output.i get error when i go to the labelling part of the algorithm.i am doing connected component labelling in my project.after the filter part the labelling part gives me the output which does not show me the output in the ila.

           when col_filter =>
                col_buf(0) <= row_out(col_count);
           		col_buf(8 downto 1) <= col_buf(7 downto 0);	
                col1 <= col_buf(0);
                col2 <= col_buf(1);
                col3 <= col_buf(2);
                col4 <= col_buf(3);
                col5 <= col_buf(4);
                col6 <= col_buf(5);
                col7 <= col_buf(6);
                col8 <= col_buf(7);
                col9 <= col_buf(8);
                col_out <= col1 or col2 or col3 or col4 or col5 or col6 or col7 or col8 or col9;
                delay_line(0) <= col_out;
                delay_line(row_width + 1 downto 1) <= delay_line(row_width downto 0);
                current_pixel  <= delay_line(0);
                left_pixel     <= delay_line(1);
                right_up_pixel <= delay_line(row_width - 1);
                up_pixel       <= delay_line(row_width);
                left_up_pixel  <= delay_line(row_width + 1);
                if current_pixel = '0' then
                   id_label := "00000000";
                elsif current_pixel = '1' then
                    if left_up_pixel = '0' and up_pixel = '0' and right_up_pixel = '0' and left_pixel = '0' then
                       if label_start = '0' then
                          id_label := "00000001";
                          label_start <= '1';
                          new_label <= id_label;
                          new_label_start <= '1';
                          label_pixel_start(conv_integer(id_label)) <= row_addr & conv_std_logic_vector(col_count + 1,10);
                       else
                          id_label := new_label + "1";
                          new_label <= id_label;
                          new_label_start <= '1';
                          label_pixel_start(conv_integer(id_label)) <= row_addr & conv_std_logic_vector(col_count + 1,10);
                       end if;
           --          elsif left_pixel = '1' then
           --          id_label := left_label;
           --          new_label_start <= '0';
                    elsif left_pixel = '1' then
                          if right_up_pixel = '1' then
                             if left_label < right_up_label then
                                id_label := left_label;
                             else
                                id_label := right_up_label;
                             end if;
                          else
                              id_label := left_label;
                          end if;
                    elsif right_up_pixel = '1' then
                          id_label := right_up_label;
                          new_label_start <= '0';
                    elsif up_pixel = '1' then
                          id_label := up_label;
                          new_label_start <= '0';
                    elsif left_up_pixel = '1' then
                          id_label := left_up_label;
                          new_label_start <= '0';
                    end if;
                end if;                    
                current_label <= id_label;
                if id_label > 0 then
                   label_pixel_end(conv_integer(id_label)) <= row_addr & conv_std_logic_vector(col_count + 1,10);
                end if;
                label_buffer(0) := id_label;
                label_buffer(1 to row_width + 1) := label_buffer(0 to row_width);
                left_up_label := label_buffer(row_width + 1);
                up_label := label_buffer(row_width);
                right_up_label := label_buffer(row_width - 1);
                left_label := label_buffer(1);           
                if current_label > "0000000" then
                  count := counter_array(conv_integer(current_label));
                  count := count + "1";
                  counter_array(conv_integer(current_label)) <= count;
                --else
                  --count := "00000000000000";
                  --counter_array(conv_integer(current_label)) <= count;
                end if;
                data_ready <= '0';
                state <= filter_loop;
           when filter_loop =>
                output(col_count) <= col_out;
                pixel_output <= col_out;
                col_count <= col_count + 1;
                if col_count = row_width-1 then
                  col_count <= 0;
                  data_ready <= '1';
                  --we <= "1";
                  --out_pixel <= output;
                  state <= addr_increment;
                else
                  state <= col_filter;
                end if;

i have attached the labelling part of the algorithm.i have 3 arrays.2 arrays as look up table and one label_buffer which stores the labels of previous pixels.

 

[TrickyDicky]

I dont quite know what you expect us to do, other than tell you to keep on debugging?
We dont have the code, we dont have the project, and we dont have the algorithm spec. All we can do is ask questions and coment on the code you have posted:

I see you're using a lot of variables? as a beginner, I would always recommend avoiding variables completly. There is nothing almost nothing you can do with a variable you cannot do with a signal, and signals are usually much safer to use as their position in the code will not (usually) affect the generated logic.

Does the RTL schematic generally match the architectural diagram you drew before you wrote any code (you did do an architectural diagram, didnt you?). If there is a missmatch - why? if you dont have an architectural diagram, why not?

Does the design meet your timing requirements? have you looked at the timing report for any failed paths?

All you have posted so far are code snippets and you now expect us to fix your mistakes. We cannot do the project for you - you need to get more specific with your questions before we can really help.

So - all I can recommend is keep on debugging. Please post more questions as they come along.

 

[sreevenkjan]

well I have posted the whole code...i am using variables because i wanted to have the register values in the same clock cycle rather than wait for a clock cycle...I did refer to a architectural diagram and follow similar structure in my program too.

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

entity filter_mytop is
    Port ( clk : in STD_LOGIC
           --rstn : in STD_LOGIC
           --data_out : out STD_LOGIC_VECTOR(37 downto 0)
          );
end filter_mytop;

architecture Behavioral of filter_mytop is
    
    -- Adding BRAM content
        
    COMPONENT blk_pic5
    PORT (
        clka : IN STD_LOGIC;
        wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
        dina : IN STD_LOGIC_VECTOR(751 DOWNTO 0);
        douta : OUT STD_LOGIC_VECTOR(751 DOWNTO 0)
      );
    END COMPONENT;
    
    constant width : integer := 7;
    constant row_width : integer := 752;
    constant addr_width : integer := 9;
    constant count_width : integer := 14;
    constant label_number : integer := 200;
    
    ---- Adding ILA component
        
    COMPONENT ila_1
      PORT (
        clk : IN STD_LOGIC;
        probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        probe1 : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
        probe2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
      );
    END COMPONENT;
    
    -- Signal declarations for bram
    signal we : std_logic_vector(0 downto 0);
    signal row_addr : std_logic_VECTOR(8 downto 0);
    signal row : std_logic_vector(751 downto 0);
    signal out_pixel : std_logic_vector(751 downto 0);
    
    -- State machine definitions for filter
    type filter_state is (addr_increment,row_filter,col_filter,filter_loop,count_output);
    signal state : filter_state := addr_increment;
    
    -- Array buffer declaration for filter 
    type array_buffer is array(1 to 9) of STD_LOGIC_VECTOR(row_width-1 DOWNTO 0);
    signal row_buf : array_buffer := (others=>(others=>'0'));
    
    -- Array buffer declaration for label
    type label_array is array(0 to row_width + 1) of std_logic_VECTOR(width downto 0);
    
    -- Array declaration for pixel label location
    type pixel_location is array(1 to label_number) of std_logic_VECTOR(addr_width*2 downto 0);
    signal label_pixel_start,label_pixel_end : pixel_location := (others=>(others => '0'));
    
    --Array declaration for label counter
    type label_counter is array(1 to label_number) of std_logic_VECTOR(count_width-1 downto 0);
    
    -- Signal declarations for counter labelling
    signal counter_array : label_counter := (others=>(others => '0'));
    signal count1,biggest_count,prev_count : std_logic_VECTOR(count_width-1 downto 0):= (others => '0');
    signal count_loop : std_logic_vector(width downto 0) := "00000001";
    signal count_number : std_logic_vector(width downto 0);
    
    -- Signal declarations for filter
    signal row1,row2,row3,row4,row5,row6,row7,row8,row9 : STD_LOGIC_VECTOR(row_width-1 DOWNTO 0):= (others => '0');
    signal row_out,output,output_buf : STD_LOGIC_VECTOR(row_width-1 DOWNTO 0):= (others=>'0');
    signal col_buf : std_logic_VECTOR(addr_width-1 downto 0):= (others=>'0');
    signal col1,col2,col3,col4,col5,col6,col7,col8,col9,col_out : std_logic := '0';
    signal data_ready : std_logic;
    signal col_count : integer range 0 to row_width-1;
    
    -- Signal declarations for component labelling
    signal current_label : std_logic_VECTOR(width downto 0):= (others => '0');
    signal current_pixel,left_pixel,up_pixel,right_up_pixel,left_up_pixel : std_logic := '0';
    --signal new_label_start : std_logic;
    signal delay_line : std_logic_vector(row_width + 1 downto 0) := (others => '0');
    signal new_label : std_logic_vector(width downto 0);
    signal data_out : STD_LOGIC_VECTOR(37 downto 0):= (others => '0');
    
    -- Signal declarations for ILA
    signal pixel_output : STD_LOGIC;
    signal probe0_data : std_logic_vector( 1 downto 0 ) := "00";
    
    signal reset_n : std_logic := '0';
    signal reset_counter : integer range 0 to (10*1024*1024-1) := 0; 

begin
    
    --Instantiating BRAM.
    
    bram : blk_pic5
        port map(
        clka => clk,  
        wea => we,   
        addra => row_addr,
        dina => out_pixel,
        douta => row);
    
    -- Instantiating ILA
       
    ila_system : ila_1
      PORT MAP (
        clk => clk,
        probe0 => probe0_data,
        probe1 => row_addr,
        probe2 => current_label
      );
              
    probe0_data <= pixel_output & reset_n;

    reset_gen : process (clk)
    begin
        if rising_edge(clk) then
            reset_counter <= reset_counter + 1;
            if reset_counter > 10000000 then
                reset_counter <= 0;
                reset_n <= not reset_n;
            end if;
        end if;
    end process;
        
    -- Filtering Process
    dilation_filter : process(clk)
        variable label_buffer     : label_array := (others=>(others => '0'));
        variable id_label         : std_logic_vector(width downto 0):= (others => '0');
        variable left_label       : std_logic_vector(width downto 0) := (others => '0');
        variable up_label         : std_logic_vector(width downto 0) := (others => '0');
        variable right_up_label   : std_logic_vector(width downto 0) := (others => '0');
        variable left_up_label    : std_logic_vector(width downto 0) := (others => '0');
        variable count,count_val  : std_logic_vector(count_width-1 downto 0);
    
    begin

    if rising_edge(clk) then
       if reset_n='0' then
           state <= addr_increment;
           row1 <= (others => '0');
           row2 <= (others => '0');
           row3 <= (others => '0');
           row4 <= (others => '0');
           row5 <= (others => '0');
           row6 <= (others => '0');
           row7 <= (others => '0');
           row8 <= (others => '0');
           row9 <= (others => '0');
           --rst <= '1';
           row_addr <= "000000000";
           state <= addr_increment;
       else
           case state is
           when addr_increment =>
                we <= "0";
                row_addr <= row_addr + "000000001";
                --if row_addr = "111011110" then   --- row = 478
                if row_addr = "111100000" then            --- row 480
                  --rst <= '1';
                  row_addr <= "000000000";
                  --state <= addr_increment;
                  data_ready <= '0';
                  state <= count_output;
                else
                  data_ready <= '0';
                  state <= row_filter;
                end if;
           
           when row_filter =>
                row_buf(1) <= row;
--                for i in 1 to 8 loop
--                    row_buf(i+1) <= row_buf(i)
--                end loop;
                row_buf(2) <= row_buf(1);
                row_buf(3) <= row_buf(2);
                row_buf(4) <= row_buf(3);
                row_buf(5) <= row_buf(4);
                row_buf(6) <= row_buf(5);
                row_buf(7) <= row_buf(6);
                row_buf(8) <= row_buf(7);
                row_buf(9) <= row_buf(8);
                row1       <= row_buf(1);
                row2       <= row_buf(2);
                row3       <= row_buf(3);
                row4       <= row_buf(4);
                row5       <= row_buf(5);
                row6       <= row_buf(6);
                row7       <= row_buf(7);
                row8       <= row_buf(8);
                row9       <= row_buf(9);
                row_out    <= row1 or row2 or row3 or row4 or row5 or row6 or row7 or row8 or row9;
                state <= col_filter;
                
           when col_filter =>
                col_buf(0) <= row_out(col_count);
           		col_buf(8 downto 1) <= col_buf(7 downto 0);	
                col1 <= col_buf(0);
                col2 <= col_buf(1);
                col3 <= col_buf(2);
                col4 <= col_buf(3);
                col5 <= col_buf(4);
                col6 <= col_buf(5);
                col7 <= col_buf(6);
                col8 <= col_buf(7);
                col9 <= col_buf(8);
                col_out <= col1 or col2 or col3 or col4 or col5 or col6 or col7 or col8 or col9;
                -- labelling part of the algorithm starts
                delay_line(0) <= col_out;
                delay_line(row_width + 1 downto 1) <= delay_line(row_width downto 0);
                current_pixel  <= delay_line(0);
                left_pixel     <= delay_line(1);
                right_up_pixel <= delay_line(row_width - 1);
                up_pixel       <= delay_line(row_width);
                left_up_pixel  <= delay_line(row_width + 1);
                if current_pixel = '0' then
                   id_label := "00000000";
                elsif current_pixel = '1' then
                    if left_up_pixel = '0' and up_pixel = '0' and right_up_pixel = '0' and left_pixel = '0' then
                       id_label := new_label + "1";
                       new_label <= id_label;
                       --new_label_start <= '1';
                       label_pixel_start(conv_integer(id_label)) <= row_addr & conv_std_logic_vector(col_count + 1,10);
           --          elsif left_pixel = '1' then
           --          id_label := left_label;
           --          new_label_start <= '0';
                    elsif left_pixel = '1' then
                          if right_up_pixel = '1' then
                             if left_label < right_up_label then
                                id_label := left_label;
                             else
                                id_label := right_up_label;
                             end if;
                          else
                              id_label := left_label;
                          end if;
                    elsif right_up_pixel = '1' then
                          id_label := right_up_label;
                          --new_label_start <= '0';
                    elsif up_pixel = '1' then
                          id_label := up_label;
                          --new_label_start <= '0';
                    elsif left_up_pixel = '1' then
                          id_label := left_up_label;
                          --new_label_start <= '0';
                    end if;
                end if;                    
                current_label <= id_label;
                if id_label > 0 then
                   label_pixel_end(conv_integer(id_label)) <= row_addr & conv_std_logic_vector(col_count + 1,10);
                end if;
                label_buffer(0) := id_label;
                label_buffer(1 to row_width + 1) := label_buffer(0 to row_width);
                left_up_label := label_buffer(row_width + 1);
                up_label := label_buffer(row_width);
                right_up_label := label_buffer(row_width - 1);
                left_label := label_buffer(1);           
                if current_label > "0000000" then
                  count_val := counter_array(conv_integer(current_label));
                  count := count_val + "1";
                  counter_array(conv_integer(current_label)) <= count;
                end if;
                data_ready <= '0';
                state <= filter_loop;
                
           when filter_loop =>
                output(col_count) <= col_out;
                pixel_output <= col_out;
                col_count <= col_count + 1;
                if col_count = row_width-1 then
                  col_count <= 0;
                  data_ready <= '1';
                  --we <= "1";
                  --out_pixel <= output;
                  state <= addr_increment;
                else
                  state <= col_filter;
                end if;
                
           when count_output =>
                count1 <= counter_array(conv_integer(count_loop));
                if count1 > prev_count then
                   biggest_count <= count1;
                   count_number <= count_loop - "1";
                else
                   biggest_count <= prev_count;
                end if;
                prev_count <= biggest_count;
                count_loop <= count_loop + "1";
                --data_out <= label_pixel_start(conv_integer(count_number)) & label_pixel_end(conv_integer(count_number));
                if count_loop = label_number then
                   state <= addr_increment;
                else
                   state <= count_output;
                end if;
           end case;
       end if; -- reset
	end if; -- clock

    end process dilation_filter;

end Behavioral;

I am not able to find the counter_array and label_pixel_start and label_pixel_End in my elaborated design..is it because I am using arrays as look up tables?..If replacing it by BRAM would solve my issue??but if i use BRAM i would be needing 2 clock cycles for reading and writing..so is there a way to avoid it??..

 

[TrickyDicky]

Ive found the problem. Your design has no outputs. Hence all logic will be removed.

- - - Updated - - -

Using arrays to store values is fine, but if you want them to map to BRAMs, you need to follow the coding guidelines from Xilinx to make sure the behaviour is correct. Otherwise it will map to registers, take a long time to compile and use a large amount of logic.

You also need to note that the logic comes from your code behaviour. Using signals in a clocked will mean you always get registers. Using variables means you can get registers or async logic depening on how you access the variables. For example, your label_buffer variable will not create a register, as it is read after it has been set. TO make it a register, you need to read the value before you set it.

 

[sreevenkjan]

Hi TrickyDicky,

I am able to observe the pixel_output in the ILA which is nothing but my col_out i.e my filtered pixel data.
but what i am not able to observe is the biggest count signal data which gives me random values.
can you tell me why is it happening differently for pixel_output which is on probe0 which i am able to observe??

 

[mrflibble]

I am not able to find the counter_array and label_pixel_start and label_pixel_End in my elaborated design..is it because I am using arrays as look up tables?..If replacing it by BRAM would solve my issue??but if i use BRAM i would be needing 2 clock cycles for reading and writing..so is there a way to avoid it??..

Assuming for the moment that they were not optimized away, the names after synthesis can sometimes be a bit non-intuitive. So you might want to look for anything that matches a *label_pixel* wildcard. If you still cannot find the instances you are looking for, time to read the synthesis warnings to see if something was optimized away.

As for "well, I have posted the whole code....", I take it you meant "well, I have posted the whole code just now for the first time". Unless "incomplete code snippets" are the same thing as "entire code" where you live.

- - - Updated - - -

Doh, never mind. I should probably refresh ye olde browser tab before posting. Optimized away? Total surprise!

 

[sreevenkjan]

Mr Flibble I have posted the complete code except for the company and engineer name and the design wrapper of the whole system ..

TrickyDicky label_buffer has been created as register in the schematic...counter_array buffer is missing in the schematic..

the algorithm which i am trying to create is a connected component labelling algorithm without merger.

 

[TrickyDicky]

Hi TrickyDicky,

I am able to observe the pixel_output in the ILA which is nothing but my col_out i.e my filtered pixel data.
but what i am not able to observe is the biggest count signal data which gives me random values.
can you tell me why is it happening differently for pixel_output which is on probe0 which i am able to observe??

I dont know which count signal/variable you are talking about.
Count is just a temporary variable that reads one value from an array, adds one and writes back to the same array in the same clock cycle, so I can garantee that counter_array has not been mapped to a memory.

 

[sreevenkjan]

yes counter_array is also missing in the schematic.so how do i correct it?...how can i read and write in the same clock cycle??

 

[TrickyDicky]

you can read and write in the same clock cycle - but not into a BRAM. You'll have to create the array out of regsiters. And it has probably optimised them all and or merged them with other things, and hence all the renaming.

Easiest thing to do - follow the RTL diagram through - you know what should connect to the counter array (count1) so follow it back from there.

The random values could be coming about because you have not reset the counter_array. Because you cannot find the counter_array in the schematic, the initialisation value may have been lost, so they will be powering up with random values. If it had been synthed as a ram it probably would have initialised properly. Safest thing to do is connect a global async reset and reset the array rather than initialising it.

 

[mrflibble]

As for reading and writing in the same clock cycle, you could use a dual port BRAM. One read port, one write port. But pleeeeeease, pretty please with sugar & cream on top, if you do read the fine manual (on BRAM resources) for the limitations. That's the only way to be sure it will meet all the requirements you didn't post about.