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If the std cell at low voltage could received a signal with the highest voltage, then no level shifter is mandatory as technology point of view.
You should need a level shifter to have a accurate timing report, because the liberty of the level shifter will be related to this voltage translation. Without that you do not know how the timing of the std cell at low voltage which received a signal at high voltage, so you don't know how the hold time will be properly fix.
This may have been touched on by the previous post... Although we say a '0' is 0V and we say the supply voltage is a '1', real circuits may have signals which do not go all the way down to zero, or all the way up to the supply level.
In the effort to reduce ambiguity, we must scale the signal so it is always recognized as being at a level which the device can tell whether it is a '1' or a '0'.
True, ambiguity is less likely for logic '0' signals. Nevertheless real circuitry does not always perform to ideal specs. A signal conceivably might not go all the way down to 0 volts. It might happen due to noise on the line, mistakes in design, mistakes in component usage, fan-out to too great a load, etc.
In any case, digital circuitry deals with logic 'High' levels as well as logic 'Low'. A designer needs to maintain agreement from each component to the next, as to what are the regions for recognizing a 'High' or a 'Low'.
If they are not in agreement, then dual clock signals can get out of sync, because of transitions being triggered at different volt levels. Etc.
There could even be a situation where one stage's 'High' level overlaps into the following stage's 'Low' level.
Various logic level formats are explored at the webpage:
'Logic signal voltage levels'