Why do I get too big library setup time?

[alexhugo]

Hi,
I do a report_timing in dc_shell and I get a huge library setup time of -123.44ns
You can see the last part of the timing report:

Can you guess why a 40nm cell (FF) should have such a huge library setup time? clock period is 2.5ns

Thanks
Alex


node_1/index_reg/D (SDFQND2BWP) 0.00 0.57 r
data arrival time 0.57

clock mck (rise edge) 2.50 2.50
clock network delay (ideal) 0.00 2.50
node_1/index_reg/CP (SDFQND2BWP) 0.00 2.50 r
library setup time -123.44 -120.94
data required time -120.94
--------------------------------------------------------------------------
data required time -120.94
data arrival time -0.57
--------------------------------------------------------------------------
slack (VIOLATED) -121.51

 

[mail4idle2]

report with transistion and capacitance also in time report that will explain to you

 

[alexhugo]

This is the new report with more information.
I don't understand how I can get rid of the library setup time.

Helps are greatly appreciated.

 

[alexhugo]

Problem is resolved.
I was using a control signal to OR with rst and reset all flops. The number of flops in terms of 100's of thousands and I couldn't set it like RST to be ideal network.