Why do FF and latch require a setup time?

[samuel_john]

SET UP TIME

hi everyone./...

i came with a very basic question....

why do FF require setup time.....if we consider a FF it would be a Master slave Latch....or a narrow pulse triggered Latch,.,,,,

so why do latch require a setup time...is it something related to Transitor parameter or gate level parameter...

any good link would also be helpful....

Also if i want to study the Transitor level architecture of FPGa where can i find it...i.e i want to find....how is FF, LUT, Mux, tristate buffer.....implemented using CMOS....Plz suggest me some link

thanks

 

[samuel_john]

Re: SET UP TIME

i would change my question to...

why is setuptime and holdtime required for a latch/FF.

 

[tlp71@hotmail.com]

Re: SET UP TIME

depending from your hardware.
In the Data sheet related you r devices you can find this info.
Bye.
G.

 

[huster]

SET UP TIME

Because all semiconductor devices have delay.

 

[samuel_john]

Re: SET UP TIME

thanks for reply...

if all semiconductor device has delay...then even.... and gate, or gate....should also have setup time.....then why is that only FF and latch is having a setup time....

rajkumar

 

[zape]

Re: SET UP TIME

From the point of view of CMOs clasical design, a D FF is composed by two latches clocked in different edges. For example, a rising edge FF, is composed by a first latch (called master latch) that when the clock is low propagates the input data to the second latch (slave latch) which is mantaining in its output the FF previous value. When a rising edge comes the output is updated by the slave latch. Setup time in this case is the maximum delay of the two input inverters (master latch) previous to the clock rising edge. Please find attached file.

Hope it clarifies.