Why Data Stobe is required?

[anandraj_pdy]

why DQS(Data stobe) is latched with DQ(Data Bus) why not with cK(clock) signal?

 

[rhaynes]

If you are talking about SDRAM interfaces then the DQS is used to register the write data into the RAM and the external interface uses the DQS to register the read data from the RAM. The reason for doing this is all about improving timing. On PCBs it's difficult to keep large numbers of traces all the same length and it is also difficult to guarantee timing to a single clock on a large number of IO pins within a chip. So this allows the wide busses to be divided up into smaller groups each with there own clock. These are called lanes on an SDRAM design. The timing on one lane is independent (within a range) of the other lanes which help improves timing margin. Also the SDRAM data is what is called source synchronous which means the clock is sent with the data to be clocked whether it's a read or write.

All this makes it more difficult to interface is a SDRAM DDR/DDR2/3/4.. But without these techniques the high clock speeds seen today would not be possible.

Does this answer your question?

Ray

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[anandraj_pdy]

Thanks for your reply....

I understood somewhat....

can u explain this concept some more details...

 

[rhaynes]

I need a more specific question. What do you need help with, basic source synchronous timing issues or specific SDRAM signals?

Ray

 

[kj.singh]

I thnk Ray has provided good explanation to your query. If you read his description while viewing timing diagram of any SDRAM/DDR memory datasheet, it should help you. The DRAM memories latch the data with DQS signals and not clock.
But during layout of the PCB, the DQS and clock should be routed relative as per the guidelines of the controller you are using.
-kjs

 

[aggpankaj2]

Definitely Ray has provided a good explanation and very accurate. Dividing the data lines into lanes including DQS and mask signals make lanes independent of each other, though whole lanes are further binded with respect to clock. The whole concept is to have a good time margin and to avoid the skew problem in fast signals.

 

[ssj]

Thanks Ray for the explanation.
I have another doubt about ONFI spec for DDR NAND. For Writes, DQS is center aligned to DQ bus while for Read DQS is aligned with DQ bus. Any specific reason for this?

-ssj

 

[rhaynes]

If you try and imagine the design required to do any other way, I think you will realize it is the way it is because it makes sense (i.e. requires the least amount of total silicon area memory+controller). Here is what I concluded.

For the writes the device would need to delay the DQS on each lane to center it in the DQ eye. But since the DQS is an intermittent clock it's not possible to use a PLL for that delay, you would have to use DLL type logic which is very area intensive. By pushing it to the controller you only need one PLL/DLL delay block which keeps the total system silicon area lowest.

I think for the reads the device could have created a delayed DQS without too much trouble. In that case the controller timing could be fixed. But I think fixing the timing would be too difficult at higher speeds so it needs to be adjustable. Since that adjustability is required in the controller there is no point in adding the delay to the device. Not having that delay in the device keeps the total system silicon area lower.

Since all my designs have been dedicated discrete SDRAM designs there are also probably more issues I haven't thought about once you get into designs using multiple DIMM modules with different length lanes, busing, and termination.


Hope that answers your question.

Ray

 

[ssj]

You are right. It really makes sense to have this difference.
I appreciate your reply. Thanks.

-ssj

 

[tdminion]

If the DQS is shifted until it samples a high clock in the DRAM (for write leveling), how is the relationship between DQS and DQ maintained while the DQS is changing phase? Is there a DLL for each memory controller DQ that uses DQS as a reference?