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Since most standard cell flops have hold time very close to 0 (much smaller than CK->Q time) so unless there is a fair amount of clock skew it is next to impossible to not meet hold time.
The hold time equation can be roughly stated as:
Tck-q + Tlogic_delay - Tskew => Thold
Worst case is when Tlogic_delay =0, the equation becomes:
Tck-q - Tskew => Thold
Now, if Tskew = 0 (pre-CTS, perfect clock tree) it becomes only Tck-q => Thold, in modern standard cell libraries this is almost always true, thus it is useless to do hold analysis before cts.
before CTS there iis no real clock network, wth ideal clock , even if you try to fix the hold(assuming some clock skew), again you need to fix them with correct values after the real clock tree is implemented . hence there is no point in trying to fix hold in pre CTS stage
I think eternal has given a good explanation using the equation.
Only after the clock has been routed it will make sense to do the hold timing check as we can now have the actual clock path delay and replace that with the ideal clock.
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