Why clocks have 50% duty cycle in many designs ?

[sandysuhy]

Clocks problem

Hi everyone,

I have seen in many designs that clock period has 50% duty cycle. What is the reason behind it.
Why cant we have different duty cycle.Can anyone help me.
Regards
Sandeep.

 

[eeeraghu]

Re: Clocks problem

That's the way to achieve performance and eliminating clock related issues, delays etc easily.

 

[eda_boy]

Re: Clocks problem

if the duty cycle of clock is something 30%, if u use latch in the ciruit then it depends upon the rise time of the clock, so if you assume the rising and falling times are different, the circuit operation becomes some critical,

suppose there is a combinational circuit between two latches,if u design the circuit such that combinational delay occurs half of the period of the clock,then synchronous will occur between the latches and combinational circuit such that the latch operates a risng time and the combinational delay is at falling time so that next latch gets the data exactly at next rising edge.

in this ciruit if u use less than 50% or morethan 50% then your circuit will malfunction

so inorder to maintain the synchronous between the latches or flipflops we generally use 50% duty cycle considering that operation of combinational circuit needs 50% of period as worst case

 

[pamulurureddy]

Clocks problem

to maintain the synchconisation we keep 50%

 

[soccer]

Clocks problem

i do not know the cause, but i think answers above are not complete. who can give more adept answer?

 

[amaccormack]

Re: Clocks problem

Having a roughly symmetric clock means that analysis is simpler: any timing path between successive clock edges can be determined to be half of the total period, no matter what those edges are. If you only ever use one egde of the clock there are less reasons to have a 50/50 clock. A PLL or DLL will typically generate a clock with 50/50 duty cycle, however, different rise/fall delays in the clock buffering tree means that this gets skewed as it is distributed around a chip.

 

[tarkyss]

Clocks problem

i think amaccormack is right

 

[alchip]

Re: Clocks problem

For double edge triggered, duty cycle is an issue such as DDR.
For single edge triggered, duty cycle is minor factor.

 

[barkha]

Re: Clocks problem

Balanced 50% Duty cycle is important in systems that use both the rising and falling clock edges it means importance for applications which are sensitive to the duty cycle or where operations are synchronized with both transitions of the clock.

 

[viv_1005]

Re: Clocks problem

Many times you use -ve edge also withing the circuit, e.g DDR. Here it is imp to have 50% duty cycle. Another thing is, for bigger asics clock tree is big and complicated. You need to add buffers to avoid skew problems. Here, if the duty cycle is not 50%, then the analysis become difficult.

 

[dBUGGER]

Clocks problem

Hi,
nowadays, processors that work on very high clock frequencies like pentium etc., use 2-phase clocks. These are a set of two non-overlapping clocks which have different duty cycles. So here in this case the duty cycle in not 50%. 50% duty cycle is not actually required in systems that are triggering on a single edge. But the fact that most oscillators give out 50% duty cycle is why you see clock with equal on and off times.

Best Regards,

 

[funster]

Re: Clocks problem

if you use only one clock edge in your system,

clock's duty cycle is not important, and if you

use both clock edge in your system, you must consider

clock's duty cycle.

best regards

Hi everyone,

I have seen in many designs that clock period has 50% duty cycle. What is the reason behind it.
Why cant we have different duty cycle.Can anyone help me.
Regards
Sandeep.

 

[wkong_zhu]

Clocks problem

1. If your design has both positive edge triggered FFs and negative triggered FFs, 50% duty cycle is very important to ensure timing closure.
2. a clock signal pass to a gate, generally, the rising time and falling time is not equal, so in CTS, you must use CLKBUF, to make sure that, when clock arrives at the FFs, the duty cycle will not change. But this is difficult to meet. The duty cycle at the FFs is a little different from the clock source. Duty cycle 50% is robust about duty cycle shift.

 

[RTL2GDSII]

Re: Clocks problem

In a design that only uses one edge of the clock(either falling or rising), duty cycle is not important. Otherwise, you have to make sure no setup/hold is violated between FFs of different clocking edge.

 

[dr_dft]

Re: Clocks problem

Even though 50% duty cycle is not required for designs triggered off one edge only, you should keep the duty cycle reasonable. 40-60 is reasonable, 10-90 is not, especially for high speed clocks.
The reason is that at very high speeds, the clock waverform may not be a full 'square function', but closer to a triangular shape. If the duty cycle is very skewed, all you get are runt pulses.

 

[Thomson]

Re: Clocks problem

As far as the timing analysis, the cycle period is used instead of the duty.

Apart from the different block using different clock edges, this is the possible case!

But i've still confusion about this cause! Maybe the duty of 50% is easily implemented in the circuit and have better characteristics.

Hope anyone can help solve this!:|

 

[alok_ky]

Clocks problem

it is always better to maintain symmetry...may be it is in layout or waveforms...it is much easier to handle symmetrical things.

 

[AlexWan]

Clocks problem

The clock that its duty clcye is 50% is stabler than other duty cycle clocks.

In the UG of PrimeTime, if the duty clcyle is so little, such as 10%, 20%, the clock may be not stable during passing into all field. Assume a clock, its duty cycle is 20%, its clock period is 10ns. So there are 2ns for clock from rising edge to falling edge. Maybe there isn't enough time for voltage changing. So in the clock tree, some high clock may be lost.

 

[zhangpengyu]

Clocks problem

Something about synchconisation and performance!

 

[Thomson]

Re: Clocks problem

Something about synchconisation and performance!

Can you specify them detailedly?

Thanks!

Thomson