Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why clock is not synthesized in DC?

Status
Not open for further replies.
What do you mean by not synthesized? Please be specific and do search in this forum first or in google.
We set the clock signal as ideal because the tool dont know the placement of the cells and many other things which is only available after placement of the design.

Thanks.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top