Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
because edge triggered circuits work mainly on the edge and a slight mismatch could mean trouble in the operation and the clock skew.... mainly due to the fact that in some circuits many blocks use the same clock....
How are we preserving the edges by ensuring that rise and fall times are same?. If we need to preserve the edges, the statement should be that rise time of all clock buffers in the same domain should be same and fall time for all clock buffers in the same domain should be same as well.
rise time and fall time being same is not a condition to use both edges of the clock. Bothe edges can be used irresepective of rise and fall time being same.
It might be a requirement for generating a 50 % duty cycle. Duty cycle can affect timing when both edges are used.
If your design totally uses positive edges it is not that important... you can use uneven buffers usually with no problem.
However, ...there is a small but here.... there is a small danger that very uneven edges, in very high frequencies close to the natural frequency of your buffer, can result in "attenuating"/muting your clock edge... but this is not something that you should usually worry about unless you are working in very high frequency...
Anyway, you shouldn't really use negative edge.. if you want the negative edge of a clock, invert it with a good buffer, make a good clock tree and use the positive edge
Think about buffers in a clock tree. If the rise time and fall time are big different, after 7 or 8 levels of tree buffers, the duty cycle at the tree leaf will be very bad. For some application that use both edges of clock (it clips the setup time) or in high speed design (clock might get muted) will have problem.