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Why can't we have intra assignment delay in Verilog code?

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msumanreddy

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why can't we have intra assignemt delay in continuous statement in the verilog code like
assign x = #5 clk
 

vinod_g

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Re: verilog code

see first here x should be declared as wire . so the value is should be calcualted at the 0ns simultion time and the valuue have to assign after 5ns .so X is net not register ,hence illegal statement
 

rakesh1234

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Re: verilog code

see first here x should be declared as wire . so the value is should be calcualted at the 0ns simultion time and the valuue have to assign after 5ns .so X is net not register ,hence illegal stateme
 

eeeraghu

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Re: verilog code

The reg data type holds a value until a new value is driven onto it in an initial or always block. The reg type can only be assigned a value in an always or initial block, and is used to apply stimulus to the inputs of the DUT. The wire type is a passive data type that holds a value driven on it by a port, assign statement or reg type. Wires can not be assigned values inside always and initial blocks.
 

aslijia

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verilog code

when synthesising, the tool will omit the timing delay automatically. so after that, assign x = #5 clk will be equal to assign x= clk.
 

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