why can't TetraMAX get right test pattern for path delay falut

[allen_eadboard]

why can't TetraMAX get right test pattern for path delay falut?

while atpg with TetraMAX for path delay fault model, it reports fault and test coverage is 100%.
Then when i simulate the test pattern in NC-verilog, it don't launch a transition in the corresponding path. And the way testing path delay is launch off capture.

The transcripts is that:
#############
read_netlist *.v
read_netlist lib.v
run_build_model *
run_drc *.spf
set_faults -model path_delay
add_delay_paths *
add_faults -all
set_atpg -capture_cycles 2
run_atpg
write_patterns

thanks.

 

[ConradATPG]

It is not clear what the problem is. My guess is that you don't really know or you english is insufficient for you to explain the problem you are seeing.

The following statement is incoherent:

it don't launch a transition in the corresponding path. And the way testing path delay is launch off capture.

Please try to explain this issue again.

 

[avinashch]

do you have your verilog model, testbench and your generated synthesised design in the same directory?

 

[dhaval4987]

Hey guys... sorry to spamming here rather than helping, but can you provide me a tutorial for tetramax?