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why cannot S/H circuit use very small capacitor ?

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iexplorer

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I simulate a S/H circuit , use capacitor low as 100f, result shows that the error is really huge , but I cannot get the reason . If using full differential archi. and CMOS transfer gate, I can cancel the charge injection.the architecture is parasite insensitive architecture , and the opamp get enough gain and SR.
 

It may because of transistor's parasitic capacitor.
So you must use larger capacitor for S/H compare to this parasitic capacitors.
 

one reason can be that the S/H thermal noise voltage is about sqrt(kT/C), which means C cannot be very small, espacially for A/D converter which requires high accuracy
 

iexplorer said:
I simulate a S/H circuit , use capacitor low as 100f, result shows that the error is really huge , but I cannot get the reason . If using full differential archi. and CMOS transfer gate, I can cancel the charge injection.the architecture is parasite insensitive architecture , and the opamp get enough gain and SR.

The size of cap used in SH often determined by three factors.
1> Themal noise, KT/C
2> Matching requirement
3> Quantization noise.
For high resolutin ADC than 10bit,the requirement of cap for KT/C noise if often overshadowed by the requirements for matching.So the minimum size requierd to get a partitular resolution overshadowed the miminum size from KT/C noise point of view.
 

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