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[SOLVED] why call instruction has highest T states in 8085?

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i 8085 microprocessor why the call instuction has highest T states for opcode fetch(i.e,6T states)?

---------- Post added at 05:12 ---------- Previous post was at 05:09 ----------

most of the instructions in 8085 are having only 4T states for the opcode fetch, why for call 6 T states?
 

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Assume at Memory Location 2000H instruction CALL 3000H is written

During a call instruction the uP pushes the current value of program counter(16 bit ie 2 byte | Here it is 2000H) to the stack and then copies the new value from the memory(specified in the instruction | Here 3000H)

So now
6 T state Opcode fetch

+ Memory write * 2 (PC pushed to stack) ( 3+3 )

+ Memory read * 2 (New value of PC fetched from memory) ( 3+3 )

ie 6 + 3 + 3 + 3 + 3 = 18 T-states.
 

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Assume at Memory Location 2000H instruction CALL 3000H is written

During a call instruction the uP pushes the current value of program counter(16 bit ie 2 byte | Here it is 2000H) to the stack and then copies the new value from the memory(specified in the instruction | Here 3000H)

So now
6 T state Opcode fetch

+ Memory write * 2 (PC pushed to stack) ( 3+3 )

+ Memory read * 2 (New value of PC fetched from memory) ( 3+3 )

ie 6 + 3 + 3 + 3 + 3 = 18 T-states.

thanks for the reply
my question is why 6 T states for opcode fetch for call instruction?

but for most of the instructions in 8085 are of 4 T states
 

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can any one tell me
why it is so for the CALL instruction? 6 T states for opcode fetch
OR
how will be the timing diagram for CALL instruction?
 

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Some instructions use a combination of addressing modes. A CALL instruction, for example, combines direct addressing and register indirect addressing. The direct address in a CALL instruction specifies the address of the desired subroutine; the register indirect address is the stack pointer. The CALL instruction pushes the current contents of the program counter into the memory location specified by the stack pointer.

Timing Effects of Addressing Modes:
Addressing modes affect both the amount of time required for executing an instruction and the amount of memory required for its storage. For example, instructions that use implied or register addressing, execute very quickly since they deal directly with the processor’s hardware or with data already present in hardware registers. Most important, however is that the entire instruction can be fetched with a single memory access. The number of memory accesses required is the single greatest factor in determining execution timing. More memory accesses therefore require more execution time. A CALL instruction for example, requires five memory accesses: three to access the entire instruction and two more to push the contents of the program counter onto the stack.

The processor can access memory once during each processor cycle. Each cycle comprises a variable number of states. The length of a state depends on the clock frequency specified for your system, and may range from 480 nanoseconds to 2 microseconds. Thus, the timing for a four state instruction may range from 1.920 microseconds through 8 microseconds. (The 8085 have a maximum clock frequency of 5 MHz and therefore a minimum state length of 200 nanoseconds.)
 
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