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why behavioral RTL verilog simulation is faster than synthesized gate level netlist

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tariq786

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Hi guys,

I want to hear from you why the synthesized gate level simulation is slower than behavioral RTL simulation by orders of magnitude?

Thanks
 

dave_59

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I would think anyone that anyone who already knows the difference between RTL and gate-level netlists would know the answer to this question.
 

tariq786

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i was expecting a good answer from you dave !
 

dave_59

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How about you think up an answer and I'll tell you if are on the right track.
 

tariq786

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okie the answer i know is that

gate-level simulation has many more events than rtl simulation. I mean at the input and output both have the same behavior but inside the design, gate-level has many more events to process than equivalent rtl.The reason for this is still not very clear to me. May be you can throw some light?
 

dave_59

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You got it.

Look at the expression

A + B

Where A and B are 32-bit numbers. In RTL, this gets evaluated directly by the CPU the simulation is running on, at the speed of a single CPU instruction. But at the gate level- each gate gets evaluated as one CPU instruction. In reality, the scheduling and propagation of new values resulting from each evaluation takes far more cycles than the actual evaluation. Many simulators optimize gate-level netlists back to their RTL equivalent to get performance, but there's only so much you can do and still preserve the timing accuracy needed in in gate-level simulation
 
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