why,asyncronous reset is prefared active low?

[ankit12345]

why,asyncronous reset is prefared active low?

 

[chiguoquan]

For the compatibilty with TTL ?

 

[ankit12345]

can u explain in detail?
Thanks for the reply

 

[WA]

Usually active lows are prefered due to noise on lines.

What I mean is that usually there are noise spike riding on logic lines. If noise is on (for example 5v (high) line, it won't matter because it is riding on 5v.

The active low activates when line goes low (usually ground) so noise is grounded.

In most TTL logic anything around 2.2V or higher is considered a high. Grounds are usually noisy so a noise spike could come within this value and activate your reset and cause you lots of unexpected results.

If you have active low, Then any noise is on the 5V line but it won't effect the logic because the noise is above active low region (usually from 0V to .7V).

Hope this helps
wa

 

[incisive]

https://digitalelectronics.blogspot.com/2005_12_01_digitalelectronics_archive.html
few answers

 

[spauls]

Because of inspurious transition due to glitch