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Why are upper Metal layers wider

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ykishore

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Why are upper Metal layers wider than the lower ones? Is that due to lithography reasons?

Say if we layout a lower layer wider than the min required and same width as one of the upper layers, which of these offer low resistance?
i.e., among a M1 of width W and M3 of same width W, which of these two has low resistance?
 

oratie

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You are right. The upper metals wider, because they have higher thickness.

So, if you draw lower and upper metals with the same width, the thicker metal (upper) will have lower resistance.

The question is : why the upper metal have higher thickness? Some reasons: they are cheaper, they have less faults (shorts/opens) during fabrication (higher yield), you need some metal layers with low resistance for routing power/ground/clock busses.
 

biju4u90

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@oratie: Suppose M1 and M3 are having same thickness too. In such a situation, will the resistance of the two layers be the same for same width? Or are there any other factors that influence the resistance, like different metals for different layers or variation in resistivity?
 

oratie

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For two metal layers with equal thickness/width/metal the resistance will be the same. Regarding the different metals for different layer - yes, it is possible. For example, the upper metal layer for bump routing (RDL - redistribution layer) has different material (Al+Pb), while others use Cu.

Just for info: usually, M1 has different (smaller) thickness than other metals.
 

dick_freebird

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Lower metal levels impact cell library and close-in routing
density so lithography there values fine pitch. Etch process
control at fine pitch wants a thinner layer, side-etch is a
control problem made worse by layer thickness / height.
Planarity also is helped by thinner lower layers, less work
for the CMP planarization steps.

A competing interest is having high current carrying capacity,
low series resistance and, for RF, low stray capacitance.
The first two are had by thicker metal, the latter by having
the layer higher above the substrate plane. Assuming you
want all these things, you do it at the uppermost one or two
levels, and you take the pain of increased minimum line width,
increased spacing.
 

Anand Cool B

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What dick_freebird said is totally right.As we go for higher level metals the thickness will be more and hence their resistance decreases.The lithography cost also increases for higher metal layers so as much as possible for sub block layouts we need to do it in lower level metals.
 

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