Why are reset synchronizers used ?

[alam.tauqueer]

Hi,

Can anyone explain me why reset synchronizer used?

And why asynchronous reset deassertion should be synchronized?

Regards,
Tauqueer

 

[sree205]

reset synchronizers

For any asynchronous signal used in a synchronous domain, there are two time constraints called recovery and removal contrainsts. These should be satisfied to ensure glitch free operation.

The resets should be synchronously deasserted to overcome removal time constraints associated with the reset.

Added after 1 minutes:

Here is a link with detailed discussion and explanation of async/sync resets

https://www.deepchip.com/items/0409-11.html

 

[alam.tauqueer]

timing constraint reset synchronizer

References are very good ...and now I got the idea why reset synchronizer used for asynchronous reset.

Thanks alot
Regards,
Tauqueer

 

[wkong_zhu]

fpga reset synchronizer

reset synchronization is used to make sure the initial condition is what you want.
If the state registers are not reset at the same clock cycle, it may crash the whole system.

 

[meanupam]

Must read. Nicely explained.


**broken link removed**

 

[ksahil]

hi...

i have one doubt that even if we synchronize the reset, then wont there be any problem when that synchronized reset is going in design and reseting a flop in which clock is skewed w.r.t clock used in reset synchronizer....

thanks

 

[meanupam]

ksahil.. yes that is a problem. Reset synchronizers are not meant to tackle this problem.
Reset synchronizers are mainly used to tackle the problem as explained in the link i posted. Its not the same if you read it more closely.

The problem you mentioned is what is a typical timing problem occurs everytime in the design and is handled by balancing each path using buffers.