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Because chip size of memory devise is defined by cell size. So you should start layout design from cell layout. To minimize it sometimes some design rules may be violated. Of course this violation should be approved by process design engeneer.
After that you should fit your row decoder/driver layout and column decoder/sense_amplifier layout to cell size.
Then you should floorplan and design the rest of circuits. You can get minimal chip size (and lower price) only by this way.
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