Why active low reset are used in Verilog?

[no_mad]

Active low reset

Hi all,

Normally, in verilog code people tend to use active low reset. Can somebody explain why??

Thanx in advance,
nomad

 

[stormwolf]

Active low reset

I always use active low reset, becase after reset , The reset signal change to high , so the reset signal will not infer by noise.

 

[IanP]

Re: Active low reset

Low active reset is maybe more common than High active reset but I can't see any particular reason why one i used more often then the other.
Good example here is the 51-family which uses High-Active Reset and so far no one have complained about it..

Reason for Active-Low lay somewhere in history and habits..

 

[no_mad]

Re: Active low reset

Reason for Active-Low lay somewhere in history and habits...

Hey, I dont think it is just an habits or some history behind it. I believe there is a reason why almost all the designer prefer active-low reset.

I agree with stromwolf. To avoid reset signal inferred by noise. Thanx

 

[eda_wiz]

Active low reset

I use only Low active Reset because the Technology library (TSMC 130nm)I am using for synthesis only has low active reset FFs...

regards

 

[nand_gates]

Re: Active low reset

I dont know whether its true or not I heared this somewhere...
The reset pin is actually pulled low inside chip. So that by mistake
if you left it open then also the chip will be in reset; and this will
keep the flops which control tri state bus drives reset so as the bus gets
hiZ. and the tri stated io's get protected.

Please confirm this..

 

[joebazoka]

Re: Active low reset

You must have in mind that bipolar transistors are inverters. If you think in this you can have an idea about why the reset signals are low active. Remember that semiconductor are builded with transistors. Regards.

 

[cklin]

Re: Active low reset

Most library supply active-low reset DFFs. It seems that larger noise margin exists in low states.

 

[smith_kang]

Re: Active low reset

active low reset is used to avoid the noise and signal interference issues in ASICs.now however active low is faster way to reset than active high.you can verify this with rise and fall time in any reference book

 

[akp494]

Re: Active low reset

May be this paper on resets may be of some help .

 

[yeewang]

Active low reset

to me, here are three reasons.
1. in CMOS technology, if I don't get it wrong, the falling edge of a signal is sharper than a rising one.
2. for TTL/LVCMOS and some other standard, floating is somehow taken as a high by circuit, which will keep the circuit working other than reset if using low-active reset.
3. Personal habbits or library implies.

 

[jitendra]

Re: Active low reset

Hi,
One possible reason is the Board design methods. Usually capacitor circuit is used for Power-On-Reset, such that the voltage at reset pin gradually goes to HIGH value. And by this time all reset activity is done.
More accurate answers are welcome.

Regards,
Jitendra