wht will output for this verilog code

[shiv_emf]

Given the following verilog code, What value of "a" is displayed ?

always@(clk)begin
a=0;
a<=1;
$display(a);
end

 

[Shurik]

Hello!!!
Cannot use in one always the blocking assignment and nonblocking assignment together!!


a=0 !!!

 

[shiv_emf]

well ....... I want output nt ur views !!
its posible to write tht code n ... or may b it cant be synthesiable .. but ths nt da issue ..

Wht will be the value of a ......... a=??

 

[echo47]

Shurik already said the correct answer.

Assuming "a" is a register ...
After each clock edge: a is set to 0, then a is displayed, then a is set to 1.

Remember that a<=1 schedules the assignment for the end of the time step.

For more info, see IEEE Std 1364-2005, section 9.2.2, Example 1.

 

[Shurik]

a will display "0" always !!!!