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Who knows about Multi-Phase clock generation using PLL/DLL?

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Alles Gute

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Multi-Phase clock generation using PLL or DLL, as shown in the figure.
How to implement the Delay Cell? I want the delay cell to be differential for good supply rejection.
 

tsb_nph

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Re: Who knows about Multi-Phase clock generation using PLL/D

Hi,
You can use a simple differential pair with PMOS triode transistors or
resistor load ( a BJT equivalent is also possible).
Refer to Section 5.3 of Chapter 5 in this thesis :
https://kabuki.eecs.berkeley.edu/~gchien/thesis/PhD/GCphdThesis.pdf

Hope that helps

Bharath
 

Alles Gute

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Re: Who knows about Multi-Phase clock generation using PLL/D

tsb_nph,
Thanks for your reply, thanks for the paper, I also have that paper and read it.
But I find if load resistor is realized by active device like MOS transistor, they more or less have some non linearity. And one problem occur (as shown in the attached figure): The non-linear load resistor makes the crossover point of input and output at different voltage level. And this makes delay between clk1 and clk2 not equal to delay between clk2 and clk3! Since delay is mesured at the same voltage level.
 

tsb_nph

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Re: Who knows about Multi-Phase clock generation using PLL/D

Alles Gute said:
tsb_nph,
Thanks for your reply, thanks for the paper, I also have that paper and read it.
But I find if load resistor is realized by active device like MOS transistor, they more or less have some non linearity. And one problem occur (as shown in the attached figure): The non-linear load resistor makes the crossover point of input and output at different voltage level. And this makes delay between clk1 and clk2 not equal to delay between clk2 and clk3! Since delay is mesured at the same voltage level.

Hi Alles Gute,
OK, I see the problem. Can't you use simple load resistors to make it a smple CMOS CML type delay element? The resistor value will determine the output signal swing and the output resistance (RC time constant at the output pretty much sets the delay, after accounting for the transistor switching time).
Another suggestion is to use appropriately sized diode connected transistor as load - not very sure of its cons, though.
A quick question on your previous design - how did you choose the gate control voltage for the triode transistor. I think there must be an optimum voltage which might prevent the non-linearity.

Bharath
 

flushrat

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Re: Who knows about Multi-Phase clock generation using PLL/D

attatchment are three differential cells
 

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